STM32F100RB STMicroelectronics, STM32F100RB Datasheet - Page 15

• Manufacturer Part Number: STM32F100RB
• Description: Mainstream Value line, ARM Cortex-M3 MCU with 128 Kbytes Flash, 24 MHz CPU, motor control and CEC functions
• Manufacturer: STMicroelectronics

Specifications of STM32F100RB

• Peripherals Supported: timers, ADC, SPIs, I2Cs, USARTs and DACs
• Conversion Range: 0 to 3.6 V
• 16-bit, 6-channel Advanced-control Timer: up to 6 channels for PWM output, dead time generation and emergency stop
• Systick Timer: 24-bit downcounter

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB
2.2.6
2.2.7
2.2.8
2.2.9
2.2.10
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 18 edge detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 80 GPIOs can be connected
to the 16 external interrupt lines.
Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-24 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example on
failure of an indirectly used external crystal, resonator or oscillator).
Several prescalers allow the configuration of the AHB frequency, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and
the APB domains is 24 MHz.
Boot modes
At startup, boot pins are used to select one of three boot options:
●
●
●
The boot loader is located in System Memory. It is used to reprogram the Flash memory by
using USART1. For further details please refer to AN2606.
Power supply schemes
●
●
●
Power supply supervisor
The device has an integrated power on reset (POR)/power down reset (PDR) circuitry. It is
always active, and ensures proper operation starting from/down to 2 V. The device remains
in reset mode when V
external reset circuit.
The device features an embedded programmable voltage detector (PVD) that monitors the
V
generated when V
DD
/V
Boot from user Flash
Boot from system memory
Boot from embedded SRAM
V
Provided externally through V
V
RCs and PLL (minimum voltage to be applied to V
used).
V
V
registers (through power switch) when V
DD
SSA
DDA
BAT
DDA
= 2.0 to 3.6 V: External power supply for I/Os and the internal regulator.
, V
= 1.8 to 3.6 V: Power supply for RTC, external clock 32 kHz oscillator and backup
power supply and compares it to the V
and V
DDA
SSA
= 2.0 to 3.6 V: External analog power supplies for ADC, DAC, Reset blocks,
DD
must be connected to V
/V
DD
DDA
is below a specified threshold, V
drops below the V
Doc ID 16455 Rev 6
DD
pins.
DD
DD
PVD
and V
is not present.
PVD
threshold and/or when V
SS
threshold. An interrupt can be
DDA
, respectively.
POR/PDR
is 2.4 V when the ADC or DAC is
, without the need for an
DD
/V
DDA
Description
is higher
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