STM32F100RB STMicroelectronics, STM32F100RB Datasheet - Page 28

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STM32F100RB

Manufacturer Part Number
STM32F100RB
Description
Mainstream Value line, ARM Cortex-M3 MCU with 128 Kbytes Flash, 24 MHz CPU, motor control and CEC functions
Manufacturer
STMicroelectronics
Datasheet

Specifications of STM32F100RB

Peripherals Supported
timers, ADC, SPIs, I2Cs, USARTs and DACs
Conversion Range
0 to 3.6 V
16-bit, 6-channel Advanced-control Timer
up to 6 channels for PWM output, dead time generation and emergency stop
Systick Timer
24-bit downcounter

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Pinouts and pin description
Table 4.
1. I = input, O = output, S = supply, HiZ= high impedance.
2. FT= 5 V tolerant.
3. Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower
4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should
5. PC13, PC14 and PC15 are supplied through the power switch and since the switch only sinks a limited amount of current
6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even after
7. Unlike in the LQFP64 package, there is no PC3 in the TFBGA64 package. The V
8. I2C2 is not present on low-density value line devices.
9. SPI2 is not present on low-density value line devices.
10. TIM4 is not present on low-density value line devices.
11. The pins number 2 and 3 in the VFQFPN36 package, 5 and 6 in the LQFP48 and LQFP64 packages and C1 and C2 in the
12. This alternate function can be remapped by software to some other port pins (if available on the used package). For more
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100 64 E4 48
90
91
92
93
94
95
96
97
98
99
number of peripherals that is included. For example, if a device has only one SPI, two USARTs and two timers, they will be
called SPI1, USART1 & USART2 and TIM2 & TIM 3, respectively. Refer to
be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).
(3 mA), the use of GPIOs PC13 to PC15 in output mode is restricted: the speed should not exceed 2 MHz with a maximum
load of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED).
reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the Battery
backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the
STMicroelectronics website: www.st.com.
TFBGA64 package are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be
remapped by software on these pins. For more details, refer to the Alternate function I/O and debug configuration section in
the STM32F10xxx reference manual.
details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available
from the STMicroelectronics website: www.st.com.
56 A4 40
57 C4 41
58 D3 42
59 C3 43
60 B4 44
61 B3 45
62 A3 46
63 D4 47
-
-
Pins
-
-
STM32F100xx pin definitions (continued)
-
-
Pin name
BOOT0
V
V
PB4
PB5
PB6
PB7
PB8
PB9
PE0
PE1
DD_3
SS_3
I/O FT
I/O
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
S
S
I
STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB
Doc ID 16455 Rev 6
(after reset)
function
NJTRST
BOOT0
V
V
Main
PB5
PB6
PB7
PB8
PB9
PE0
PE1
SS_3
DD_3
(3)
I2C1_SCL
I2C1_SDA
I2C1_SMBA / TIM16_BKIN
TIM16_CH1
Table 2 on page
TIM4_CH3
TIM4_CH4
TIM4_CH2
TIM17_CH1
TIM4_ETR
TIM16_CH1N
REF+
(12)
Default
(12)
Alternate functions
/ TIM4_CH1
functionality is provided instead.
/ TIM17_CH1N
(12)
(10)(12)
(10)(12)
(10)(12)
/ CEC
11.
(10)
(12)
/
/
(12)
(10)(12)
(3)(4)
PB4 / TIM3_CH1
USART1_RX
USART1_TX
TIM3_CH2 /
SPI1_MISO
SPI1_MOSI
I2C1_SDA
I2C1_SCL
Remap

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