STM32F100VD STMicroelectronics, STM32F100VD Datasheet - Page 30

• Manufacturer Part Number: STM32F100VD
• Description: Mainstream Value line, ARM Cortex-M3 MCU with 384 Kbytes Flash, 24 MHz CPU, motor control and CEC functions
• Manufacturer: STMicroelectronics

Specifications of STM32F100VD

• Peripherals Supported: timers, ADC, SPIs, I2Cs, USARTs and DACs
• Conversion Range: 0 to 3.6 V
• One 16-bit, 6-channel Advanced-control Timer: up to 6 channels for PWM output, dead time generation and emergency stop
• Systick Timer: 24-bit downcounter

Pinouts and pin descriptions
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2. FT = 5 V tolerant.
3. Function availability depends on the chosen device.
4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one
5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited
6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup
7. This alternate function can be remapped by software to some other port pins (if available on the used
8. For the LQFP64 package, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset,
9. For devices delivered in LQFP64 packages, the FSMC function is not available.
Table 5.
peripheral should be enabled at a time through the peripheral clock enable bit (in the corresponding RCC
peripheral clock enable register).
amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not
exceed 2 MHz with a maximum load of 30 pF and these IOs must not be used as a current source (e.g. to
drive an LED).
registers even after reset (because these registers are not reset by the main reset). For details on how to
manage these IOs, refer to the Battery backup domain and BKP register description sections in the
STM32F100xx reference manual, available from the STMicroelectronics website: www.st.com.
package). For more details, refer to the Alternate function I/O and debug configuration section in the
STM32F100xx reference manual, available from the STMicroelectronics website: www.st.com.
however the functionality of PD0 and PD1 can be remapped by software on these pins. For the LQFP100
and LQFP144 packages, PD0 and PD1 are available by default, so there is no need for remapping. For
more details, refer to Alternate function I/O and debug configuration section in the STM32F100xx
reference manual.
PF10
PF11
PF12
PF13
Pins
PE2
PE3
PE4
PE5
PE6
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PF8
PF9
FSMC pin definition
NOR/PSRAM/SRAM
A23
A19
A20
A21
A22
A0
A1
A2
A3
A4
A5
A6
A7
Doc ID 15081 Rev 5
FSMC
STM32F100xC, STM32F100xD, STM32F100xE
NOR/PSRAM Mux
A23
A19
A20
A21
A22
LQFP100
Yes
Yes
Yes
Yes
Yes
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(1)