ST72324J6 STMicroelectronics, ST72324J6 Datasheet - Page 137

• Manufacturer Part Number: ST72324J6
• Description: 8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST72324J6

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator, clock security system and bypass for external clock
• Four Power Saving Modes: Halt, Active-Halt, Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• 16-bit Timer A With: 1 input capture, 1 output compare, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

CONTROL PIN CHARACTERISTICS (Cont’d)
Figure 77. RESET pin protection when LVD is enabled.
Figure 78. RESET pin protection when LVD is disabled.
1. The reset network protects the device against parasitic resets.
2. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device
can be damaged when the ST7 generates an internal reset (LVD or watchdog).
3. Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below
the V
4. Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must ensure
that the current sunk on the RESET pin (by an external pull-up for example) is less than the absolute maximum value
specified for I
5. When the LVD is enabled, it is mandatory not to connect a pull-up resistor. A 10nF pull-down capacitor is recommended
to filter noise on the reset line.
6. In case a capacitive power supply is used, it is recommended to connect a1MΩ pull-down resistor to the RESET pin
to discharge any residual voltage induced by this capacitive power supply (this will add 5µA to the power consumption of
the MCU).
7. Tips when using the LVD:
Required
– 1. Check that all recommendations related to ICCCLK and reset circuit have been applied (see notes above)
– 2. Check that the power supply is properly decoupled (100nF + 10µF close to the MCU). Refer to AN1709. If this
– 3. The capacitors connected on the RESET pin and also the power supply are key to avoiding any start-up margin-
EXTERNAL
EXTERNAL
CIRCUIT
cannot be done, it is recommended to put a 100nF + 1MΩ pull-down on the RESET pin.
ality. In most cases, steps 1 and 2 above are sufficient for a robust solution. Otherwise: replace 10nF pull-down on
the RESET pin with a 5µF to 20µF capacitor.”
RESET
IL
USER
RESET
max. level specified in
Recommended
INJ(RESET)
Recommended
0.01µF
in
V
DD
Section 12.2.2 on page
0.01µF
0.01µF
Section
1MΩ
Optional
(note 6)
V
DD
12.10.1. Otherwise the reset will not be taken into account internally.
4.7kΩ
117.
V
V
DD
DD
R
R
ON
ON
Filter
Filter
1)2)3)4)5)6)7)
1)2)3)4)
GENERATOR
GENERATOR
PULSE
PULSE
ST72324Jx ST72324Kx
INTERNAL
RESET
INTERNAL
RESET
WATCHDOG
WATCHDOG
LVD RESET
ST72XXX
ST72XXX
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