ST72324J6 STMicroelectronics, ST72324J6 Datasheet - Page 151

• Manufacturer Part Number: ST72324J6
• Description: 8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST72324J6

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator, clock security system and bypass for external clock
• Four Power Saving Modes: Halt, Active-Halt, Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• 16-bit Timer A With: 1 input capture, 1 output compare, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

ST72324 DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)
OPTION BYTE 1
OPT7= PKG1 Pin package selection bit
This option bit selects the package.
Note: On the chip, each I/O port has 8 pads. Pads
that are not bonded to external pins are in input
pull-up configuration after reset. The configuration
of these pads must be kept at reset state to avoid
added current consumption.
OPT6 = RSTC RESET clock cycle selection
This option bit selects the number of CPU cycles
applied during the RESET phase and when exiting
HALT mode. For resonator oscillators, it is advised
to select 4096 due to the long crystal stabilization
time.
0: Reset phase with 4096 CPU cycles
1: Reset phase with 256 CPU cycles
OPT5:4 = OSCTYPE[1:0] Oscillator Type
These option bits select the ST7 main clock
source type.
OPT3:1 = OSCRANGE[2:0] Oscillator range
When the resonator oscillator type is selected,
Resonator Oscillator
Reserved
Internal RC Oscillator
External Source
Version
K
J
Clock Source
Selected Package
TQFP44 / SDIP42
TQFP32 / SDIP32
1
0
0
1
1
OSCTYPE
PKG1
0
0
1
0
1
1
0
these option bits select the resonator oscillator
current source corresponding to the frequency
range of the used resonator. Otherwise, these bits
are used to select the normal operating frequency
range.
OPT0 = PLL OFF PLL activation
This option bit activates the PLL which allows mul-
tiplication by two of the main input clock frequency.
The PLL must not be used with the internal RC os-
cillator. The PLL is guaranteed only with an input
frequency between 2 and 4MHz.
0: PLL x2 enabled
1: PLL x2 disabled
CAUTION: the PLL can be enabled only if the
“OSC RANGE” (OPT3:1) bits are configured to
“MP - 2~4MHz”. Otherwise, the device functionali-
ty is not guaranteed.
LP
MP
MS
HS
Typ. Freq. Range
8~16MHz
1~2MHz
2~4MHz
4~8MHz
ST72324Jx ST72324Kx
2
0
0
0
0
OSCRANGE
1
0
0
1
1
151/164
0
0
1
0
1
1