ST72324J6 STMicroelectronics, ST72324J6 Datasheet - Page 57

• Manufacturer Part Number: ST72324J6
• Description: 8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST72324J6

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator, clock security system and bypass for external clock
• Four Power Saving Modes: Halt, Active-Halt, Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• 16-bit Timer A With: 1 input capture, 1 output compare, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d)
10.2.5 Low Power Modes
10.2.6 Interrupts
The MCC/RTC interrupt event generates an inter-
rupt if the OIE bit of the MCCSR register is set and
the interrupt mask in the CC register is not active
(RIM instruction).
Note:
The MCC/RTC interrupt wakes up the MCU from
ACTIVE-HALT mode, not from HALT mode.
10.2.7 Register Description
MCC CONTROL/STATUS REGISTER (MCCSR)
Read/Write
Reset Value: 0000 0000 (00h
Bit 7 = MCO Main clock out selection
This bit enables the MCO alternate function on the
PF0 I/O port. It is set and cleared by software.
0: MCO alternate function disabled (I/O pin free for
1: MCO alternate function enabled (f
Note: To reduce power consumption, the MCO
function is not active in ACTIVE-HALT mode.
MCO CP1
WAIT
ACTIVE-
HALT
HALT
Time base overflow
event
general-purpose I/O)
port)
Mode
Interrupt Event
7
No effect on MCC/RTC peripheral.
MCC/RTC interrupt cause the device to exit
from WAIT mode.
No effect on MCC/RTC counter (OIE bit is
set), the registers are frozen.
MCC/RTC interrupt cause the device to exit
from ACTIVE-HALT mode.
MCC/RTC counter and registers are frozen.
MCC/RTC operation resumes when the
MCU is woken up by an interrupt with “exit
from HALT” capability.
CP0
SMS
Event
Flag
OIF
Description
TB1
Control
Enable
OIE
Bit
)
TB0
from
Wait
CPU
Exit
Yes
OIE
on I/O
No
from
Exit
Halt
OIF
0
1)
Bit 6:5 = CP[1:0] CPU clock prescaler
These bits select the CPU clock prescaler which is
applied in the different slow modes. Their action is
conditioned by the setting of the SMS bit. These
two bits are set and cleared by software
Bit 4 = SMS Slow mode select
This bit is set and cleared by software.
0: Normal mode. f
1: Slow mode. f
See
MAIN CLOCK CONTROLLER WITH REAL TIME
CLOCK AND BEEPER (MCC/RTC)
tails.
Bit 3:2 = TB[1:0] Time base control
These bits select the programmable divider time
base. They are set and cleared by software.
A modification of the time base is taken into ac-
count at the end of the current period (previously
set) to avoid an unwanted time shift. This allows to
use this time base as a real time clock.
Bit 1 = OIE Oscillator interrupt enable
This bit set and cleared by software.
0: Oscillator interrupt disabled
1: Oscillator interrupt enabled
This interrupt can be used to exit from ACTIVE-
HALT mode.
When this bit is set, calling the ST7 software HALT
instruction enters the ACTIVE-HALT power saving
mode
Prescaler
Counter
200000
16000
32000
80000
f
Section 8.2 SLOW MODE
CPU
.
in SLOW mode
f
f
f
f
OSC2
OSC2
OSC2
OSC2
f
OSC2
20ms
50ms
/ 16
CPU
4ms
8ms
/ 2
/ 4
/ 8
=4MHz f
CPU
Time Base
is given by CP1, CP0
=
ST72324Jx ST72324Kx
f
OSC2
OSC2
10ms
25ms
2ms
4ms
=8MHz
CP1
and
0
0
1
1
Section 10.2
for more de-
TB1
0
0
1
1
CP0
57/164
0
1
0
1
TB0
0
1
0
1
1