ST72324J6 STMicroelectronics, ST72324J6 Datasheet - Page 59

• Manufacturer Part Number: ST72324J6
• Description: 8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST72324J6

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator, clock security system and bypass for external clock
• Four Power Saving Modes: Halt, Active-Halt, Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• 16-bit Timer A With: 1 input capture, 1 output compare, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

10.3 16-BIT TIMER
10.3.1 Introduction
The timer consists of a 16-bit free-running counter
driven by a programmable prescaler.
It may be used for a variety of purposes, including
pulse length measurement of up to two input sig-
nals (input capture) or generation of up to two out-
put waveforms (output compare and PWM).
Pulse lengths and waveform periods can be mod-
ulated from a few microseconds to several milli-
seconds using the timer prescaler and the CPU
clock prescaler.
Some ST7 devices have two on-chip 16-bit timers.
They are completely independent, and do not
share any resources. They are synchronized after
a MCU reset as long as the timer clock frequen-
cies are not modified.
This description covers one or two 16-bit timers. In
ST7 devices with two timers, register names are
prefixed with TA (Timer A) or TB (Timer B).
10.3.2 Main Features
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The Block Diagram is shown in
*Note: Some timer pins may not be available (not
bonded) in some ST7 devices. Refer to the device
pin out description.
– 2 dedicated 16-bit registers
– 2 dedicated programmable signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
– 2 dedicated 16-bit registers
– 2 dedicated active edge selection signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
Programmable prescaler: f
Overflow status flag and maskable interrupt
External clock input (must be at least 4 times
slower than the CPU clock speed) with the choice
of active edge
1 or 2 Output Compare functions each with:
1 or 2 Input Capture functions each with:
Pulse width modulation mode (PWM)
One pulse mode
Reduced Power Mode
5 alternate functions on I/O ports (ICAP1, ICAP2,
OCMP1, OCMP2, EXTCLK)*
CPU
divided by 2, 4 or 8.
Figure
35.
When reading an input signal on a non-bonded
pin, the value will always be ‘1’.
10.3.3 Functional Description
10.3.3.1 Counter
The main block of the Programmable Timer is a
16-bit free running upcounter and its associated
16-bit registers. The 16-bit registers are made up
of two 8-bit registers called high & low.
Counter Register (CR):
Alternate Counter Register (ACR)
These two read-only 16-bit registers contain the
same value but with the difference that reading the
ACLR register does not clear the TOF bit (Timer
overflow flag), located in the Status register, (SR),
(see note at the end of paragraph titled 16-bit read
sequence).
Writing in the CLR register or ACLR register resets
the free running counter to the FFFCh value.
Both counters have a reset value of FFFCh (this is
the only value which is reloaded in the 16-bit tim-
er). The reset value of both counters is also
FFFCh in One Pulse mode and PWM mode.
The timer clock depends on the clock control bits
of the CR2 register, as illustrated in
Control
peats every 131072, 262144 or 524288 CPU clock
cycles depending on the CC[1:0] bits.
The timer frequency can be f
or an external frequency.
Caution: In Flash devices, Timer A functionality
has the following restrictions:
– TAOC2HR and TAOC2LR registers are write
– Input Capture 2 is not implemented
– The corresponding interrupts cannot be used
only
(ICF2, OCF2 forced by hardware to zero)
– Counter High Register (CHR) is the most sig-
– Counter Low Register (CLR) is the least sig-
– Alternate Counter High Register (ACHR) is
– Alternate Counter Low Register (ACLR) is the
nificant byte (MS Byte).
nificant byte (LS Byte).
the most significant byte (MS Byte).
least significant byte (LS Byte).
Bits. The value in the counter register re-
ST72324Jx ST72324Kx
CPU
/2, f
Table 16 Clock
CPU
/4, f
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CPU
/8
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