ST72521AR9 STMicroelectronics, ST72521AR9 Datasheet - Page 136

• Manufacturer Part Number: ST72521AR9
• Description: 8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, FIVE TIMERS, SPI, SCI, I2C, CAN INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST72521AR9

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• Four Power Saving Modes: Halt, Active-Halt, Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, external clock input on one timer, PWM and pulse generator modes
• 8-bit Pwm Auto-reload Timer With: 2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector

ST72F521, ST72521B
CONTROLLER AREA NETWORK (Cont’d)
10.8.4 Register Description
The CAN registers are organized as 6 general pur-
pose registers plus 5 pages of 16 registers span-
ning the same address space and primarily used
for message and filter storage. The page actually
selected is defined by the content of the Page Se-
lection Register.
10.8.4.1 General Purpose Registers
INTERRUPT STATUS REGISTER (ISR)
Read/Write
Reset Value: 00h
Bit 7 = RXIF3 Receive Interrupt Flag for Buffer 3
−
Set by hardware to signal that a new error-free mes-
sage is available in buffer 3.
Cleared by software to release buffer 3.
Also cleared by resetting bit RDY of BCSR3.
Bit 6 = RXIF2 Receive Interrupt Flag for Buffer 2
−
Set by hardware to signal that a new error-free
message is available in buffer 2.
Cleared by software to release buffer 2.
Also cleared by resetting bit RDY of BCSR2.
Bit 5 = RXIF1 Receive Interrupt Flag for Buffer 1
−
Set by hardware to signal that a new error-free mes-
sage is available in buffer 1.
Cleared by software to release buffer 1.
Also cleared by resetting bit RDY of BCSR1.
136/215
RXIF3 RXIF2 RXIF1
Read/Clear
Read/Clear
Read/Clear
7
TXIF
SCIF
ORIF
TEIF
EPND
0
Bit 4 = TXIF Transmit Interrupt Flag
−
Set by hardware to signal that the highest priority
message queued for transmission has been suc-
cessfully transmitted.
Cleared by software.
Bit 3 = SCIF Status Change Interrupt Flag
−
Set by hardware to signal the reception of a domi-
nant bit while in standby mode. In Run mode this bit
is set when EPVS is set or reset (refer to
CAN Error State
receive error when ESCI=1.
Cleared by software.
Bit 2 = ORIF Overrun Interrupt Flag
−
Set by hardware to signal that a message could not
be stored because no receive buffer was available.
Cleared by software.
Bit 1 = TEIF Transmit Error Interrupt Flag
−
Set by hardware to signal that an error occurred dur-
ing the transmission of the highest priority message
queued for transmission.
Cleared by software.
Bit 0 = EPND Error Interrupt Pending
−
Set by hardware when at least one of the three error
interrupt flags SCIF, ORIF or TEIF is set.
Reset by hardware when all error interrupt flags
have been cleared.
Caution:
Interrupt flags are reset by writing a “0” to the cor-
responding bit position. The appropriate way con-
sists in writing an immediate mask or the one’s com-
plement of the register content initially read by the
interrupt handler. Bit manipulation instruction
BRES should never be used due to its read-modify-
write nature.
Read/Clear
Read/Clear
Read/Clear
Read/Clear
Read Only
Diagram). This bit also signals any
Figure 71.