ST72521AR9 STMicroelectronics, ST72521AR9 Datasheet - Page 154

• Manufacturer Part Number: ST72521AR9
• Description: 8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, FIVE TIMERS, SPI, SCI, I2C, CAN INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST72521AR9

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• Four Power Saving Modes: Halt, Active-Halt, Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, external clock input on one timer, PWM and pulse generator modes
• 8-bit Pwm Auto-reload Timer With: 2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector

ST72F521, ST72521B
CONTROLLER AREA NETWORK (Cont’d)
Workaround Description
The bus-off entry works correctly in almost all cas-
es, only when REC is greater than 127 a bus-off
will not be recognized by pCAN. Therefore the
pCAN bus-off signalling (BOFF) is still used but it
needs to be complemented by monitoring TEC by
software.
To detect the bus-off condition by software the ap-
plication has to monitor the value of the TEC reg-
ister periodically. An overflow signals a bus-off
condition. When a bus-off condition has been de-
tected the application must execute the following
sequence to recover from bus-off properly: the ap-
plication stops pCAN by clearing the RUN bit in the
CANCSR register resets all pending transmission
by clearing the LOCK bit in the BCSR register and
starts it again by setting the RUN bit.
To detect the bus-off condition properly, the TEC
monitoring period must be lower than the time be-
tween two overflows. As the problem only occurs
when pCAN is in Error Passive State (REC > 127)
pCAN will continuously try to send a SOF followed
by an Error Passive Flag and a Suspend Trans-
mission. This leads to 26 (1 + 6 + 8 + 3 + 8) bit
times. Each time TEC is incremented by 8, hence
154/215
*
/* INITIALISATION
/************************************************/
unsigned char TECReg=0; //Previous value of TEC
unsigned char BusOffFlag=0; //Set to one if bus-off
/************************************************/
/* BUS-OFF MONITORING SEQUENCE
/************************************************/
if( (CANCSR & BOFF) || ( CANTECR+1 < TECReg) )
{
}
else
{
}
***********************************************/
TECReg = CANTECR;
BusOffFlag = 1;
to reach 256 the sequence must be executed 32
times. Under these conditions the shortest se-
quence leading to a TEC overflow lasts 832 bit
times.
Depending on the baudrate the application will
have to adapt the monitoring period, for example
at 500kbps the period must be less than 1600us.
The ‘C’ code below shows an implementation ex-
ample of the monitoring sequence. This code is
called periodically as described above.
To detect the overflow, the test condition must
take into account that TEC might also have been
decremented due to a successful transmission. So
an overflow condition is detected:
IF the current TEC value is lower than the previous
TEC value
AND the difference is greater than the number of
possible successful transmissions during the mon-
itoring period.
In the example above, one message can be sent,
therefore one is added to CANTECR.