ST72521AR9 STMicroelectronics, ST72521AR9 Datasheet - Page 40

• Manufacturer Part Number: ST72521AR9
• Description: 8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, FIVE TIMERS, SPI, SCI, I2C, CAN INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST72521AR9

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• Four Power Saving Modes: Halt, Active-Halt, Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, external clock input on one timer, PWM and pulse generator modes
• 8-bit Pwm Auto-reload Timer With: 2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector

ST72F521, ST72521B
7.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7:6 = IS1[1:0] ei2 and ei3 sensitivity
The interrupt sensitivity, defined using the IS1[1:0]
bits, is applied to the following external interrupts:
- ei2 (port B3..0)
- ei3 (port B7..4)
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
Bit 5 = IPB Interrupt polarity for port B
This bit is used to invert the sensitivity of the port B
[3:0] external interrupts. It can be set and cleared
by software only when I1 and I0 of the CC register
are both set to 1 (level 3).
0: No sensitivity inversion
1: Sensitivity inversion
Bit 4:3 = IS2[1:0] ei0 and ei1 sensitivity
The interrupt sensitivity, defined using the IS2[1:0]
bits, is applied to the following external interrupts:
40/215
IS11 IS10
IS11 IS10
IS11
0
0
1
1
0
0
1
1
7
IS10
0
1
0
1
0
1
0
1
Falling edge only
Rising edge only
IPB
Falling edge &
IPB bit =0
low level
External Interrupt Sensitivity
External Interrupt Sensitivity
IS21
Falling edge & low level
Rising and falling edge
Rising and falling edge
Falling edge only
Rising edge only
IS20
IPA
Falling edge only
Rising edge only
Rising edge
& high level
IPB bit =1
TLIS TLIE
0
- ei0 (port A3..0)
- ei1 (port F2..0)
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
Bit 2 = IPA Interrupt polarity for port A
This bit is used to invert the sensitivity of the port A
[3:0] external interrupts. It can be set and cleared
by software only when I1 and I0 of the CC register
are both set to 1 (level 3).
0: No sensitivity inversion
1: Sensitivity inversion
Bit 1 = TLIS TLI sensitivity
This bit allows to toggle the TLI edge sensitivity. It
can be set and cleared by software only when
TLIE bit is cleared.
0: Falling edge
1: Rising edge
Bit 0 = TLIE TLI enable
This bit allows to enable or disable the TLI capabil-
ity on the dedicated pin. It is set and cleared by
software.
0: TLI disabled
1: TLI enabled
Note: a parasitic interrupt can be generated when
clearing the TLIE bit.
IS21 IS20
IS21 IS20
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Falling edge only
Rising edge only
Falling edge &
IPA bit =0
low level
External Interrupt Sensitivity
External Interrupt Sensitivity
Falling edge & low level
Rising and falling edge
Rising and falling edge
Falling edge only
Rising edge only
Falling edge only
Rising edge only
Rising edge
& high level
IPA bit =1