ST72521AR9 STMicroelectronics, ST72521AR9 Datasheet - Page 152

• Manufacturer Part Number: ST72521AR9
• Description: 8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, FIVE TIMERS, SPI, SCI, I2C, CAN INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST72521AR9

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• Four Power Saving Modes: Halt, Active-Halt, Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, external clock input on one timer, PWM and pulse generator modes
• 8-bit Pwm Auto-reload Timer With: 2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector

ST72F521, ST72521B
CONTROLLER AREA NETWORK (Cont’d)
The worst case is when the abort request is done
when the transmission has just started. In this
case the LOCK bit cannot be reset as long as the
BUSY bit is set, this means until the end of the
frame. So the application will wait for READY to be
reset during the whole frame and in this case the
worst case will be the longest frame the applica-
tion is expected to transmit.
Figure 81. Abort with the software work-around
- by NRTX, BUSY and LOCK
Using the software work-around the worst case
occurs in the arbitration lost case. If the abort is re-
quested just after pCAN has lost the arbitration
then the application has to wait for the next falling
edge of the BUSY bit before the LOCK bit can be
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TX RQST
ABORT RQST
CAN TX
CAN RX
LOCK
READY
BUSY
NRTX
reset. If the next arbitration is won by pCAN then
the BUSY bit will be reset by the end of the suc-
cessful transmission. The longest time the applica-
tion has to wait in this case is the time of the long-
est message expected on the bus (minus identifi-
er) plus the longest message expected to be trans-
mitted by the application. This roughly double the
time the application may have to wait before the
abort sequence is performed.
10.8.5.4 WKPS Functionality
Due to a fix implemented to solve the “Unexpected
Message Transmission” issue (see
10.8.5.3) the WKPS functionality has been modi-
fied as follows in Flash ST72F521 devices:
Flash
ST72F521
Rev R
ROM
ST72521 All
revisions
Device
WKPS bit does not generate a wakeup
pulse. It is used to synchronize the re-
set of the LOCK bit (see
Work-around - Devices with Hardware
Fix (ST72F521 rev “R”):” on page
WKPS bit functions according to the
datasheet description.
Modification
“Software
Section
148)