ST72361J6 STMicroelectronics, ST72361J6 Datasheet - Page 44

• Manufacturer Part Number: ST72361J6
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72361J6

• Hdflash Endurance: 100 cycles, data retention 40 years at 85°C
• 5 Power Saving Modes: Halt, Auto Wake Up From Halt, Active Halt, Wait and Slow

ST72361
POWER SAVING MODES (Cont’d)
8.6.1 Register Description
AWUFH CONTROL/STATUS REGISTER
(AWUCSR)
Read / Write (except bit 2 read only)
Reset Value: 0000 0000 (00h)
Bits 7:3 = Reserved.
Bit 2 = AWUF Auto Wake-Up Flag
This bit is set by hardware when the AWU module
generates an interrupt and cleared by software on
reading AWUCSR.
0: No AWU interrupt occurred
1: AWU interrupt occurred
Bit 1 = AWUM Auto Wake-Up Measurement
This bit enables the AWU RC oscillator and con-
nects its output to the ICAP1 input of the 16-bit tim-
er. This allows the timer to be used to measure the
AWU RC oscillator dispersion and then compen-
sate this dispersion by providing the right value in
the AWUPR register.
0: Measurement disabled
1: Measurement enabled
Bit 0 = AWUEN Auto Wake-Up From Halt Enabled
This bit enables the Auto Wake-Up From Halt fea-
ture: once HALT mode is entered, the AWUFH
wakes up the microcontroller after a time delay de-
fined by the AWU prescaler value. It is set and
cleared by software.
Table 11. AWU Register Map and Reset Values
44/225
Address
7
0
002Bh
002Ch
(Hex.)
0
AWUCSR
Reset Value
AWUPR
Reset Value
Register
0
Label
0
AWUPR7
0
7
0
1
AWU
F
AWUPR6
AWU
6
0
1
M
AWU
AWUPR5
EN
0
5
0
1
0: AWUFH (Auto Wake-Up From Halt) mode disa-
1: AWUFH (Auto Wake-Up From Halt) mode ena-
AWUFH PRESCALER REGISTER (AWUPR)
Read / Write
Reset Value: 1111 1111 (FFh)
Bits 7:0 = AWUPR[7:0] Auto Wake-Up Prescaler
These 8 bits define the AWUPR Dividing factor (as
explained below:
In AWU mode, the period that the MCU stays in
Halt Mode (t
This prescaler register can be programmed to
modify the time that the MCU stays in Halt mode
before waking up automatically.
Note: If 00h is written to AWUPR, depending on
the product, an interrupt is generated immediately
after a HALT instruction or the AWUPR remains
unchanged.
AWU
AWUPR4
PR7
bled
bled
7
AWUPR[7:0
4
0
1
t
AWU
FEh
FFh
00h
01h
AWU
PR6
...
AWUPR3
=
AWU
AWU
PR5
]
64
3
0
1
×
in
AWUPR
AWU
Figure
PR4
AWUPR2
AWUF
Forbidden (See note)
2
0
1
×
AWU
PR3
------------------------- -
f
30) is defined by
Dividing factor
AWURC
1
AWUPR1
AWU
254
255
AWUM
PR2
...
1
+
1
0
1
t
RCSTRT
AWU
PR1
AWUPR0
AWUEN
AWU
0
0
1
PR0
0