ST72361J6 STMicroelectronics, ST72361J6 Datasheet - Page 46

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ST72361J6

Manufacturer Part Number
ST72361J6
Description
8-bit MCU
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST72361J6

Hdflash Endurance
100 cycles, data retention 40 years at 85°C
5 Power Saving Modes
Halt, Auto Wake Up From Halt, Active Halt, Wait and Slow
ST72361
I/O PORTS (Cont’d)
Figure 32. I/O Port General Block Diagram
Table 12. I/O Port Mode Options
Legend: NI - not implemented
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Input
Output
REGISTER
ACCESS
INTERRUPT
SOURCE (ei
EXTERNAL
DDR SEL
OR SEL
Off - implemented not activated
On - implemented and activated
DR SEL
Floating with/without Interrupt
Pull-up with/without Interrupt
Push-pull
Open Drain (logic level)
True Open Drain
Configuration Mode
DDR
OR
x
DR
)
ALTERNATE
OUTPUT
ALTERNATE
ENABLE
If implemented
1
0
1
0
Pull-Up
Off
On
Off
NI
Note: The diode to V
true open drain pads. A local protection between
the pad and V
vice against positive stress.
N-BUFFER
PULL-UP
CONDITION
P-Buffer
Off
On
Off
NI
SS
SCHMITT
TRIGGER
CMOS
is implemented to protect the de-
V
DD
DD
NI (see note)
to V
is not implemented in the
On
P-BUFFER
(see table below)
DD
V
Diodes
DD
DIODES
(see table below)
PULL-UP
(see table below)
ALTERNATE
ANALOG
INPUT
to V
INPUT
PAD
On
SS

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