MAX9260 Maxim, MAX9260 Datasheet
MAX9260
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MAX9260 Summary of contents
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... UART link between the serializer and deserializer. The host electronic control unit (ECU) or microcontroller (FC) resides either on the MAX9259 (for video display the MAX9260 (for image sens- ing). In addition, the control channel enables ECU/FC control of peripherals in the remote side of the serial link ...
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... OUT+, OUT- to AGND (MAX9259) ......................-0.5V to +1.9V IN+, IN- to AGND (MAX9260) ..............................-0.5V to +1.9V LMN_ to GND (MAX9259) (60kI source impedance) ................................-0.5V to +3.9V All Other Pins to GND (MAX9259) ....... -0.5V to (IOVDD + 0.5V) All Other Pins to IOGND (MAX9260) ... -0.5V to (IOVDD + 0.5V) OUT+, OUT- Short Circuit to Ground or Supply (MAX9259) .................................................Continuous IN+, IN- Short Circuit to Ground or Supply (MAX9260) .................................................Continuous ...
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Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel MAX9259 DC ELECTRICAL CHARACTERISTICS (continued 1.7V to 1.9V, V DVDD AVDD IOVDD Typical values are DVDD AVDD PARAMETER SYMBOL ...
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Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel MAX9259 AC ELECTRICAL CHARACTERISTICS ( 1.7V to 1.9V, V DVDD AVDD IOVDD Typical values are DVDD AVDD PARAMETER SYMBOL PARALLEL ...
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... Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel MAX9260 DC ELECTRICAL CHARACTERISTICS ( 3.0V to 3.6V, V DVDD AVDD IOVDD Typical values are DVDD AVDD PARAMETER SYMBOL SINGLE-ENDED INPUTS (ENABLE, INT, PWDN, SSEN, BWS, ES, DRS, MS, CDS, EQS, DCS) High-Level Input Voltage ...
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... Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel MAX9260 DC ELECTRICAL CHARACTERISTICS (continued 3.0V to 3.6V, V DVDD AVDD IOVDD Typical values are DVDD AVDD PARAMETER SYMBOL DIFFERENTIAL OUTPUTS FOR REVERSE CONTROL CHANNEL (IN+, IN-) Differential High Output Peak V Voltage, (V ...
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... Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel MAX9260 AC ELECTRICAL CHARACTERISTICS ( 3.0V to 3.6V, V DVDD AVDD IOVDD Typical values are DVDD AVDD PARAMETER SYMBOL PARALLEL CLOCK OUTPUT (PCLKOUT) Clock Frequency f PCLKOUT Clock Duty Cycle Clock Jitter 2 I C/UART PORT TIMING ...
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... Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel MAX9260 AC ELECTRICAL CHARACTERISTICS (continued 3.0V to 3.6V, V DVDD AVDD IOVDD Typical values are DVDD AVDD PARAMETER SYMBOL OUTPUT TIMING WS Jitter t SCK Jitter t AJ-SCK Audio Skew Relative to Video SCK, SD, WS Rise-and-Fall Time ...
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... PCLKOUT FREQUENCY (MHz) SERIAL LINK SWITCHING PATTERN WITH 14dB PREEMPHASIS (PARALLEL BIT RATE = 104MHz, 10m STP CABLE) MAX9259/60 toc08 3.12Gbps 250.0mV -250.0mV 52.00ps/div OUTPUT POWER SPECTRUM vs. PCLKOUT FREQUENCY (MAX9260 SPREAD ON, MAX9259 SPREAD OFF 42MHz PCLKOUT -10 0% SPREAD -20 -30 -40 -50 -60 ...
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... TQFN (8mm x 8mm x 0.75mm) *CONNECT EP TO GROUND PLANE Pin Configurations MAX9260 EP TQFP (10mm × 10mm × 1mm) 28 CDS IOVDD 25 ...
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... Control-Direction Selection. Control-link-direction selection input requires external 33 28 CDS pulldown or pullup resistors. Set CDS = low for FC use on the MAX9259 side of the serial link. Set CDS = high for FC use on the MAX9260 side of the serial link. Power-Down. Active-low power-down input requires external pulldown or pullup 34 29 PWDN resistors ...
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... LFLT = low indicates a line fault. LFLT is high impedance when PWDN = low. Interrupt Output to Indicate Remote Side Requests. INT = low upon power-up and when PWDN = low. A transition on the INT input of the MAX9260 toggles the MAX9259’s INT output. Data-Rate Select. Data-rate range-selection input requires external pulldown or pullup resistors ...
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... Control-Direction Selection. Control-link-direction selection input requires external pull- 4 CDS down or pullup resistors. Set CDS = low for FC use on the MAX9259 side of the serial link. Set CDS = high for FC use on the MAX9260 side of the serial link. GPIO0. Open-drain general-purpose input/output with internal 60kI pullup resistors to 5 GPIO0 IOVDD ...
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... IOVDD. In UART mode, TX/SCL is the Tx output of the MAX9259’s UART mode, TX/SCL is the SCL output of the MAX9260’s I Power-Down. Active-low power-down input requires external pulldown or pullup resis- tors. Error. Active-low open-drain video data error output with internal pullup to IOVDD. ...
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... LMN1 CLKDIV DET 8B/10B CML ENCODE PARITY TERM MAX9259 REV CH 2 UART SERIALIZER SPREAD CDR PLL PLL EQ CLKDIV 8B/10B CML DECODE PARITY TERM MAX9260 REV CH 2 UART DESERIALIZER Functional Diagram OUT+ OUT- STP CABLE (Z = 50) 0 IN- IN+ 15 ...
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Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel OUT- V OS(-) OUT+ V OD(-) (OUT+) - (OUT-) Figure 1. MAX9259 Serial Output Parameters OUT OUT- Figure 2. Output Waveforms at OUT+ and OUT- 16 _____________________________________________________________________________________ ...
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Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel OUTPUT LOGIC (OUT+) LFLT OUTPUT LOGIC (OUT-) Figure 3. Fault-Detector Circuit NOTE: PCLKIN PROGRAMMED FOR RISING LATCH EDGE. Figure 4. MAX9259 Worst-Case Pattern Input ______________________________________________________________________________________ MAX9259 45.3kI* LMN0 LMN1 ...
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Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel PCLKIN t F Figure 5. MAX9259 Parallel Input Clock Requirements t R TX/ SCL RX/ SDA Figure Timing Parameters 800mV Figure 7. Differential ...
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Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel PCLKIN DIN_ Figure 8. MAX9259 Input Setup-and-Hold Times DIN_ N N+1 PCLKIN OUT+/- Figure 9. MAX9259 Serializer Delay ______________________________________________________________________________________ V IH MIN V IL MAX t SET V IH ...
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Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel PCLKIN REVERSE CONTROL CHANNEL Figure 10. MAX9259 Link Startup Time PCLKIN PWDN POWERED DOWN REVERSE CONTROL CHANNEL DISABLED Figure 11. MAX9259 Power-Up Delay WS SCK SD 2 Figure 12. ...
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... R Figure 13. MAX9260 Reverse Control-Channel Output Parameters IN IN- _ Figure 14. MAX9260 Test Circuit for Differential Input Measurement ______________________________________________________________________________________ MAX9260 REVERSE CONTROL-CHANNEL TRANSMITTER 0 0 IN+ PCLKOUT V ID(P) IN DOUT_ NOTE: PCLKOUT PROGRAMMED FOR RISING LATCH EDGE ...
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... Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel PCLKOUT Figure 16. MAX9260 Clock Output High-and-Low Times Figure 17. MAX9260 Output Rise-and-Fall Times SERIAL-WORD LENGTH SERIAL WORD N IN+/- FIRST BIT LAST BIT DOUT_ PARALLEL WORD N-2 PCLKOUT NOTE: PCLKOUT PROGRAMMED FOR RISING LATCHING EDGE. ...
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... Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel Figure 19. MAX9260 Lock Time Figure 20. MAX9260 Power-Up Delay WS SCK SD 2 Figure 21. MAX9260 Output I S Timing Parameters ______________________________________________________________________________________ IN+ - IN- t LOCK LOCK PWDN MUST BE HIGH IN+/- V PWDN IH1 t PU LOCK DVA ...
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... S port supports The FC configures various operating conditions of the GMSL through registers in the MAX9259/MAX9260. The default device addresses stored in the R0 and R1 registers of the MAX9259/MAX9260 are 0x80 and 0x90, respectively. Write to the R0/R1 registers in both devices to change the device address of the MAX9259 or MAX9260. POWER-UP DEFAULT SETTINGS ...
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... Table 2. MAX9260 Power-Up Default Register Map (see Table 19) REGISTER POWER-UP DEFAULT ADDRESS (hex) (hex) 0x00 0x80 0x01 0x90 0x02 0x1F or 0x5F ______________________________________________________________________________________ POWER-UP DEFAULT SETTINGS ...
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... Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel Table 2. MAX9260 Power-Up Default Register Map (see Table 19) (continued) REGISTER POWER-UP DEFAULT ADDRESS (hex) (hex) 0x03 0x00 0x03, 0x13, 0x83, or 0x04 0x93 0x05 0x28 or 0x29 0x06 0x0F 0x07 0x54 0x08 ...
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... INTERCHANGEABLE ACCORDINGLY ON BOTH SIDES OF THE LINK. Figure 22. 24-Bit Mode Serial Link Data Format ______________________________________________________________________________________ nal through the serial link. The MAX9260 deserializer recovers the embedded serial clock and then samples, decodes, and descrambles the data onto the paral- lel output bus. Figures 22 and 23 show the serial-data packet format prior to scrambling and 8B/10B coding ...
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... Parallel Data-Rate Selection The MAX9259/MAX9260 use the DRS inputs to set the parallel data rate. Set DRS high to use a low-speed par- allel data rate in the range of 6.25MHz to 12.5MHz (32-bit mode) or 8.33MHz to 16.66MHz (24-bit mode). Set DRS low for normal operation with parallel data rates higher than 12 ...
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... The FC uses the control link to send and receive control data over the STP link simultaneously with the high-speed data. Configuring the CDS pin allows the FC to control the link from either the MAX9259 or the MAX9260 side to sup- port video-display or image-sensing applications. The control link between the FC and the MAX9259 or ...
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... PARITY STOP START 1 Figure 27. ACK Byte (0xC3) The MAX9259/MAX9260 UART-to-I faces with devices that do not require register address- es, such as the MAX7324 GPIO expander. Change the communication method of the I I2CMETHOD bit. I2CMETHOD = 1 sets command-byte- only mode, while I2CMETHOD = 0 sets normal mode where the first byte in the data stream is the register address ...
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... S : MASTER TO SLAVE Figure 28. Format Conversion between UART and I UART-TO CONVERSION OF WRITE PACKET (I2CMETHOD = 1) MAX9259/MAX9260 SYNC FRAME DEVICE REGISTER ADDRESS MAX9259/MAX9260 PERIPHERAL 1 S DEV ID 2 UART-TO-I C CONVERSION OF READ PACKET (I2CMETHOD = 1) MAX9259/MAX9260 SYNC FRAME DEVICE REGISTER ADDRESS ...
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... The INT of the MAX9259 is the interrupt output and the INT of the MAX9260 is the interrupt input. The interrupt output on the MAX9259 follows the transitions at the interrupt input of the MAX9260. This interrupt function supports remote-side functions such as touch-screen peripherals, remote power-up, or remote monitoring ...
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... Set the MAX9259 SSEN input high to select 0.5% spread 9.4 at power-up and SSEN input low to select no spread at 10.7 power-up. Set the MAX9260 SSEN input high to select 2% spread at power-up and SSEN input low to select no spread at power-up. The state of SSEN is latched upon 11.7 power-up or when resuming from power-down mode. ...
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... DRS = DRS pin input value ( Parallel clock frequency (12.5MHz to 104MHz) PCLK_ MOD = Modulation coefficient given in Table 11 for the MAX9259 and Table 12 for the MAX9260 SDIV = 6-bit (MAX9259) or 5-bit (MAX9260) SDIV setting, manually programmed by the FC SDIV UPPER LIMIT (deci- mal ...
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... The MAX9260 exits sleep mode after locking to the serial data and sets SLEEP = 0. If after 8ms the deserial- izer does not lock to the input serial data, the MAX9260 goes back to sleep, and the internal sleep bit remains uncleared (SLEEP = 1). ...
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... Normal is disabled. Set SEREN = 1 or CLINKEN = 1 in the MAX9259 to start the serial link. MAX9260 starts in sleep mode. Link autostarts upon MAX9259 power-up. Use this case when the MAX9260 powers up before the MAX9259. CLINKEN = 0 OR SEREN = 1 CONFIG LINK CONFIG LINK UNLOCKED OPERATING ...
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... Image-Sensing Applications For image-sensing applications, with remote camera unit(s), connect the FC to the deserializer (MAX9260) and set CDS = high for both the MAX9259 and MAX9260. The MAX9260 powers up normally (SLEEP = 0) and con- tinuously tries to lock to a valid serial input. Table 14 summarizes the two startup cases, based on the state of the MAX9259 AUTOS pin ...
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... POWER-OFF POWER-OFF Figure 32. MAX9259 State Diagram, CDS = High (Camera Application) POWER-ON IDLE (REVERSE CHANNEL ACTIVE) NO SIGNAL DETECTED PWDN = LOW OR ALL STATES POWER-OFF Figure 33. MAX9260 State Diagram, CDS = High (Camera Application) 38 _____________________________________________________________________________________ 0 1 SLEEP = 0, POWER-ON WAKE-UP IDLE SEREN = 0 SEREN = 1, PCLKIN RUNNING SLEEP = 0, ...
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... MAX9260 are set to low, and for the later case, the CDS pins are set to high. However, if the CDS pin of the MAX9259 is low and the CDS pin of the MAX9260 is high, then the MAX9259/MAX9260 can both connect to FCs simultaneously. In such a case, the FCs on either side can communicate with the MAX9259/MAX9260 UART protocol ...
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... D[3:0] of the MAX9259. The fault-detector thresh- old voltages are referenced to the MAX9259 ground. Additional passive components set the DC level of the cable (Figure 3). If the MAX9259 and MAX9260 grounds are different, the link DC voltage during normal operation can vary and cross one of the fault-detection thresholds. ...
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... Power-Supply Circuits and Bypassing The MAX9259 uses an AVDD and DVDD of 1.7V to 1.9V. The MAX9260 uses an AVDD and DVDD of 3.0V to 3.6V. All single-ended inputs and outputs on the MAX9259/ Table 17. Suggested Connectors and Cables for GMSL SUPPLIER JAE Electronics, Inc ...
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... UNDER TEST tolerance for electronic systems. Serial outputs on the MAX9259 and serial inputs on the MAX9260 meet ISO 10605 ESD protection and IEC 61000-4-2 ESD protec- tion. All other pins meet the Human Body Model ESD tolerances. The Human Body Model discharge compo- ...
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Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel Table 18. MAX9259 Register Table (see Table 1 for Default Value Details) REGISTER BITS NAME ADDRESS D[7:1] SERID 0x00 D0 — D[7:1] DESID 0x01 D0 — D[7:5] SS 0x02 ...
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Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel Table 18. MAX9259 Register Table (see Table 1 for Default Value Details) (continued) REGISTER BITS NAME ADDRESS D7 SEREN D6 CLINKEN D5 PRBSEN 0x04 D4 SLEEP D[3:2] INTTYPE D1 ...
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Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel Table 18. MAX9259 Register Table (see Table 1 for Default Value Details) (continued) REGISTER BITS NAME ADDRESS D7 I2CMETHOD D6 DISFPLL D[5:4] CMLLVL 0x05 D[3:0] PREEMP 0x06 D[7:0] — ...
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... Table 18. MAX9259 Register Table (see Table 1 for Default Value Details) (continued) REGISTER BITS NAME ADDRESS D7 SETINT 0x0D D[6:4] — D[3:0] — 0x1E D[7:0] ID D[7:4] — 0x1F D[3:0] REVISION X = Don’t care. Table 19. MAX9260 Register Table REGISTER BITS NAME ADDRESS D[7:1] SERID 0x00 D0 — D[7:1] DESID 0x01 D0 — D[7: — D4 AUDIOEN ...
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... Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel Table 19. MAX9260 Register Table (continued) REGISTER BITS NAME ADDRESS D[7:6] AUTOFM 0x03 D5 — D[4:0] SDIV D7 LOCKED D6 OUTENB D5 PRBSEN D4 SLEEP 0x04 D[3:2] INTTYPE D1 REVCCEN D0 FWDCCEN ______________________________________________________________________________________ VALUE FUNCTION Calibrate spread-modulation rate only once 00 after locking ...
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... Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel Table 19. MAX9260 Register Table (continued) REGISTER BITS NAME ADDRESS D7 I2CMETHOD D[6:5] HPFTUNE D4 PDHF 0x05 D[3:0] EQTUNE D7 DISSTAG D6 AUTORST D5 DISINT D4 INT 0x06 D3 GPIO1OUT D2 GPIO1 D1 GPIO0OUT D0 GPIO0 48 _____________________________________________________________________________________ VALUE FUNCTION conversion sends the register address ...
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... Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel Table 19. MAX9260 Register Table (continued) REGISTER BITS NAME ADDRESS 0x07 D[7:0] — 0x08 D[7:0] — 0x09 D[7:0] — 0x0A D[7:0] — 0x0B D[7:0] — 0x0C D[7:0] ERRTHR 0x0D D[7:0] DECERR 0x0E D[7:0] PRBSERR D7 MCLKSRC 0x12 D[6:0] MCLKDIV 0x1E D[7:0] ID D[7:4] — ...
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... Package Information For the latest package outline information and land patterns (footprints www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. ...
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... Added Patent Pending to Features Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 2011 Maxim Integrated Products © ...