MAX9260 Maxim, MAX9260 Datasheet - Page 12

• Manufacturer Part Number: MAX9260
• Description: The MAX9259/MAX9260 chipset presents Maxim's gigabit multimedia serial link (GMSL) technology
• Manufacturer: Maxim

Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
12
TQFP
40, 41
_____________________________________________________________________________________
36
37
38
43
44
45
46
47
48
—
PIN
34, 35
TQFN
31
32
33
37
38
39
40
41
42
—
TX/SCL
NAME
OUT+
LMN1
OUT-,
LMN0
SSEN
LFLT
BWS
DRS
INT
ES
EP
Transmit/Serial Clock. UART transmit or I
pullup to IOVDD. In UART mode, TX/SCL is the Tx output of the MAX9259’s UART. In I
mode, TX/SCL is the SCL output of the MAX9259’s I
Spread-Spectrum Enable. Serial link spread-spectrum enable input requires external
pulldown or pullup resistors. The state of SSEN latches upon power-up or when resuming
from power-down mode (PWDN = low). Set SSEN = high for Q0.5% spread spectrum on
the serial link. Set SSEN = low to use the serial link without spread spectrum.
Line-Fault Monitor Input 1 (see Figure 3 for details)
Differential CML Output -/+. Differential outputs of the serial link.
Line-Fault Monitor Input 0 (see Figure 3 for details)
Line Fault. Active-low open-drain line-fault output with a 60kI internal pullup resistor.
LFLT = low indicates a line fault. LFLT is high impedance when PWDN = low.
Interrupt Output to Indicate Remote Side Requests. INT = low upon power-up and when
PWDN = low. A transition on the INT input of the MAX9260 toggles the MAX9259’s INT
output.
Data-Rate Select. Data-rate range-selection input requires external pulldown or pullup
resistors. Set DRS = high for parallel input data rates of 8.33MHz to 16.66MHz (24-bit
mode) or 6.25MHz to 12.5MHz (32-bit mode). Set DRS = low for parallel input data rates
of 16.66MHz to 104MHz (24-bit mode) or 12.5MHz to 78MHz (32-bit mode).
Edge Select. PCLKIN trigger edge-selection input requires external pulldown or pullup
resistors. Set ES = low to trigger on the rising edge of PCLKIN. Set ES = high to trigger on
the falling edge of PCLKIN.
Bus-Width Select. Parallel input bus-width selection input requires external pulldown or
pullup resistors. Set BWS = low for 24-bit bus mode. Set BWS = high for 32-bit bus mode.
Exposed Pad. EP internally connected to AGND (TQFP package) or AGND and GND
(TQFN package). MUST externally connect EP to the AGND plane to maximize thermal
and electrical performance.
MAX9259 Pin Description (continued)
FUNCTION
2
C serial-clock output with internal 30kI
2
C master.
2
C