MAX9260 Maxim, MAX9260 Datasheet - Page 27

• Manufacturer Part Number: MAX9260
• Description: The MAX9259/MAX9260 chipset presents Maxim's gigabit multimedia serial link (GMSL) technology
• Manufacturer: Maxim

Figure 22. 24-Bit Mode Serial Link Data Format
The parallel bus uses two selectable bus widths, 24
bits and 32 bits. BWS selects the bus width according
to Table 3. In 24-bit mode, DIN21–DIN28 are not used
and are internally pulled down. For both modes, SD,
SCK, and WS pins are dedicated for I
assignments of the first 21 or 29 signals are interchange-
able and appear in the same order at both sides of the
serial link. In image-sensing applications, disabling the
I
internal registers) allows the MAX9259 to serialize three
10-bit camera data streams through DIN[0:28] plus SD
inputs. The parallel bus accepts data clock rates from
8.33MHz to 104MHz for the 24-bit mode and 6.25MHz to
78MHz for the 32-bit mode.
The MAX9259 high-speed data serial output uses
CML signaling with programmable preemphasis and
AC-coupling. The MAX9260 high-speed receiver uses
AC-coupling and programmable channel equalization.
Together, the GMSL operates at up to 3.125Gbps over
STP cable lengths up to 15m.
The MAX9259 serializer scrambles and encodes the
parallel input bits, and sends the 8B/10B coded sig-
Table 3. Bus-Width Selection Using BWS
2
S audio channel (through the MAX9259 and MAX9260
BWS INPUT STATE
NOTE: LOCATIONS OF THE RGB DATA AND CONTROL SIGNALS ARE
INTERCHANGEABLE ACCORDINGLY ON BOTH SIDES OF THE LINK.
DIN0
DIN1
Serial Link Signaling and Data Format
High
Low
18-BIT
Gigabit Multimedia Serial Link with Spread
DATA
RGB
Spectrum and Full-Duplex Control Channel
______________________________________________________________________________________
DIN17 DIN18 DIN19 DIN20
Parallel Inputs and Outputs
24 BITS
BUS WIDTH
HSYNC,
VSYNC,
DE
24
32
CHANNEL BIT
2
S audio data. The
AUDIO
ACB
CHANNEL BIT
CONTROL-
FORWARD
FCC
CHECK BIT
PACKET
PARITY
PCB
nal through the serial link. The MAX9260 deserializer
recovers the embedded serial clock and then samples,
decodes, and descrambles the data onto the paral-
lel output bus. Figures 22 and 23 show the serial-data
packet format prior to scrambling and 8B/10B coding.
For the 24-bit or 32-bit mode, the first 21 or 29 serial
bits come from DIN[20:0] or DIN[28:0], respectively.
The audio channel bit (ACB) contains an encoded audio
signal derived from the three I
WS). The forward control channel (FCC) bit carries the
forward control data. The last bit (PCB) is the parity bit of
the previous 23 or 31 bits.
The MAX9259/MAX9260 use the reverse control channel
to send I
direction of the video stream from the deserializer to
the serializer. The reverse control channel and forward
video data coexist on the same twisted pair forming a
bidirectional link. The reverse control channel operates
independently from the forward control channel. The
reverse control channel is available 500Fs after power-
up. The MAX9259 temporarily disables the reverse con-
trol channel for 350Fs after starting/stopping the forward
serial link.
Figure 23. 32-Bit Mode Serial Link Data Format
NOTE: LOCATIONS OF THE RGB DATA AND CONTROL SIGNALS ARE
INTERCHANGEABLE ACCORDINGLY ON BOTH SIDES OF THE LINK.
DIN0 DIN1
DIN[0:20]/DOUT[0:20], WS, SCK, SD
DIN[0:28]/DOUT[0:28], WS, SCK, SD
PARALLEL BUS SIGNALS USED
RGB DATA
2
24-BIT
C/UART and interrupt signals in the opposite
DIN23 DIN24 DIN25 DIN26 DIN27 DIN28 ACB FCC PCB
Reverse Control Channel
32 BITS
HSYNC,
VSYNC,
DE
2
S inputs (SD, SCK, and
ADDITIONAL
CONTROL
VIDEO
DATA/
BITS
CHANNEL
AUDIO
BIT
CONTROL-
FORWARD
CHANNEL
BIT
CHECK BIT
PACKET
PARITY
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