MAX9260 Maxim, MAX9260 Datasheet - Page 49

• Manufacturer Part Number: MAX9260
• Description: The MAX9259/MAX9260 chipset presents Maxim's gigabit multimedia serial link (GMSL) technology
• Manufacturer: Maxim

Table 19. MAX9260 Register Table (continued)
X = Don’t care.
REGISTER
ADDRESS
VIDEO
UART
AUDIO
0x0A
0x0B
0x0C
0x0D
0x07
0x08
0x09
0x0E
0x12
0x1E
0x1F
ECU
HSYNC
VSYNC
PCLK
Gigabit Multimedia Serial Link with Spread
RGB
SCK
TX
RX
WS
SD
Spectrum and Full-Duplex Control Channel
LFLT
IMS
INT
D[7:0]
D[7:0]
D[7:0]
D[7:0]
D[7:0]
D[7:0]
D[7:0]
D[7:0]
D[6:0]
D[7:0]
D[7:4]
D[3:0]
BITS
______________________________________________________________________________________
D7
PCLKIN
DIN(0:27)
DIN28
CDS
AUTOS
RX/SDA
TX/SCL
LFLT
INT
MS
WS
SCK
SD
MCLKSRC
PRBSERR
REVISION
MCLKDIV
DECERR
ERRTHR
MAX9259
NAME
—
—
—
—
—
ID
—
LMN1
LMN0
OUT+
OUT-
45.3kI
4.99kI
XXXXXXXX
XXXXXXXX
XXXXXXXX
01010100
00110000
11001000
00010010
00100000
00000010
XXXXXXX
0000000
VALUE
1.8V
XXXX
0000
0
1
45.3kI
4.99kI
49.9kI
Reserved
Reserved
Reserved
Reserved
Reserved
Error threshold for decoding errors. ERR =
low when DECERR > ERRTHR.
Decoding error counter. This counter
remains zero while the device is in PRBS
test mode.
PRBS error counter
MCLK derived from PCLKOUT (see Table 5)
MCLK derived from internal oscillator
MCLK disabled
MCLK divider
Device identifier
(MAX9260 = 0x02)
Reserved
Device revision
49.9kI
Typical Application Circuit
IN+
IN-
FUNCTION
MAX9260
DOUT28/MCLK
DOUT(0:27)
PCLKOUT
RX/SDA
TX/SCL
LOCK
CDS
SCK
INT
WS
SD
PCLK
RGB
HSYNC
VSYNC
TO PERIPHERALS
SCL
SDA
WS
SCK
SD
MCLK
(read only)
(read only)
(read only)
(read only)
(read only)
DEFAULT
01010100
00110000
11001000
00010010
00100000
00000000
00000000
00000000
00000010
0000000
MAX9850
VALUE
0000
0
DISPLAY
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