MAX9260 Maxim, MAX9260 Datasheet - Page 40

• Manufacturer Part Number: MAX9260
• Description: The MAX9259/MAX9260 chipset presents Maxim's gigabit multimedia serial link (GMSL) technology
• Manufacturer: Maxim

Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
recognizes the UART sync pattern. For example, when
lowering the UART frequency from 1Mbps to 100kbps,
first send data at 333kbps and then at 100kbps to have
reduction ratios of 3 and 3.333, respectively.
Connect the LOCK output to the INT input of the
MAX9260 to loopback LOCK to the MAX9259. The
interrupt output on the MAX9259 follows the transitions
at the LOCK output of the MAX9260. Reverse-channel
communication does not require an active forward link
to operate and accurately tracks the LOCK status of the
video link. LOCK asserts for video link only and not for
the configuration link.
The MAX9260 has two open-drain GPIOs available.
GPIO1OUT and GPIO0OUT (0x06 D3, D1) set the output
state of the GPIOs. The GPIO input buffers are always
enabled. The input states are stored in GPIO1 and
GPIO0 (0x06 D2, D0). Set GPIO1OUT/GPIO0OUT to 1
when using GPIO1/GPIO0 as an input.
The line-fault detector in the MAX9259 monitors for line
failures such as short to ground, short to power supply,
and open link for system fault diagnosis. Figure 3 shows
the required external resistor connections. LFLT = low
when a line fault is detected and LFLT = high when the
line returns to normal. The line-fault type is stored in
0x08 D[3:0] of the MAX9259. The fault-detector thresh-
old voltages are referenced to the MAX9259 ground.
Additional passive components set the DC level of the
cable (Figure 3). If the MAX9259 and MAX9260 grounds
are different, the link DC voltage during normal operation
can vary and cross one of the fault-detection thresholds.
For the fault-detection circuit, select the resistor’s power
rating to handle a short to the battery. Table 15 lists the
mapping for line-fault types.
Table 15. MAX9259 Line-Fault Mapping
40
REGISTER
ADDRESS
_____________________________________________________________________________________
0x08
D[3:2]
D[1:0]
BITS
LOCK Output Loopback
Line-Fault Detection
LFNEG
LFPOS
NAME
MAX9260 GPIOs
VALUE
00
01
10
11
00
01
10
11
Negative cable wire shorted to battery
Negative cable wire shorted to ground
Normal operation
Negative cable wire open
Positive cable wire shorted to battery
Positive cable wire shorted to ground
Normal operation
Positive cable wire open
Table 16. Staggered Output Delay
The MAX9260 staggers the parallel data outputs to
reduce EMI and noise. Staggering outputs also reduce
the power-supply transient requirements. By default,
the deserializer staggers outputs according to Table
16. Disable output staggering through the DISSTAG bit
(0x06 D7)
Both I
to provide a logic-high level. There are tradeoffs between
power dissipation and speed, and a compromise must
be made in choosing pullup resistor values. Every device
connected to the bus introduces some capacitance even
when the device is not in operation. I
rise times to go from low to high (30% to 70%) for fast
mode, which is defined for data rates up to 400kbps (see
the I
table for details). To meet the fast-mode rise-time
requirement, choose the pullup resistors so that rise time
t
are not recognized if the transition time becomes too
R
DOUT11–DOUT15,
DOUT16–DOUT20,
DOUT21, DOUT22
DOUT23, DOUT24
DOUT25, DOUT26
DOUT27, DOUT28
DOUT6–DOUT10,
= 0.85 x R
DOUT0–DOUT5,
2
PCLKOUT
2
C specifications in the Electrical Characteristics
OUTPUT
C/UART open-drain lines require pullup resistors
Choosing I
PULLUP
Staggered Parallel Data Outputs
LINE-FAULT TYPE
x C
DISSTAG = 0
2
C/UART Pullup Resistors
OUTPUT DELAY RELATIVE
BUS
0.75
0.5
1.5
0
1
< 300ns. The waveforms
TO DOUT0 (ns)
2
C specifies 300ns
DISSTAG = 1
0
0
0
0
0