TMP86xy45UG Toshiba, TMP86xy45UG Datasheet
TMP86xy45UG
Specifications of TMP86xy45UG
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TMP86xy45UG Summary of contents
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Bit Microcontroller TLCS-870/C Series TMP86C845UG ...
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... Unintended Usage of Toshiba products listed in this document shall be made at the customer's own risk. 021023_B The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations ...
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Difference between TMP86C845 and TMP86Cx47 series TMP86C847UG ROM 8192bytes (MASK) RAM 512bytes I/O port 35 pins Package(Body size) LQFP44(10x10mm) Minumum command execution time Supply Voltage 16-bit timer counter: 1ch Timer counter 8-bit timer counter: 2ch Time base timer 1ch Watch ...
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TMP86C845UG ...
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Date Revision 2006/6/13 1 2006/6/29 2 2006/6/29 3 2006/8/3 4 2008/8/29 5 Revision History First Release Periodical updating. No change in contents. Periodical updating. No change in contents. Contents Revised Contents Revised ...
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Caution in Setting the UART Noise Rejection Time When UART is used, settings of RXDNC are limited depending on the transfer clock specified by BRG. The com- bination "O" is available but please do not select the combination "–". The ...
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...
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Table of Contents TMP86C845UG 1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Using data transfer instructions 3.4.3 Interrupt return ........................................................................................................................................ 40 3.5 Software Interrupt (INTSW ...
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Function ...
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Recommended Operating Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 12.3 DC ...
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... The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by impli- cation or otherwise under any patent or patent rights of TOSHIBA or others. 021023_C • ...
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Features Single clock mode Dual clock mode 10. Low power consumption operation STOP mode: Oscillation stops. (Battery/Capacitor back-up.) SLOW1 mode: Low power consumption operation using low-frequency clock.(High-frequency clock stop.) SLOW2 mode: Low power consumption operation using low-frequency clock.(High-frequency clock ...
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Pin Assignment VAREF AVDD AVSS P13 P14 21 35 P15(INT3 P16 P40 19 37 P41 P17 18 38 P42 P07(INT4 P43 P06 P44 P05(SI P45 P04(SO P46 ...
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Block Diagram 1.3 Block Diagram Figure 1-2 Block Diagram Page 4 TMP86C845UG ...
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Pin Names and Functions Table 1-1 Pin Names and Functions(1/2) Pin Name Pin Number P07 17 INT4 P06 16 SCK P05 15 SI P04 14 SO P03 13 P02 12 P01 TC4 11 PDO4/PWM4/PPG4 P00 10 INT0 P17 18 ...
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Pin Names and Functions Table 1-1 Pin Names and Functions(2/2) Pin Name P34 AIN4 P33 AIN3 P32 AIN2 P31 AIN1 P30 AIN0 P47 P46 P45 P44 P43 P42 P41 P40 XIN XOUT RESET TEST VAREF AVDD AVSS VDD VSS ...
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Operational Description 2.1 CPU Core Functions The CPU core consists of a CPU, a system clock controller, and an interrupt controller. This section provides a description of the CPU core, the program memory, the data memory, and the reset ...
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System Clock Controller Example :Clears RAM to “00H”. (TMP86C845UG) SRAMCLR: 2.2 System Clock Controller The system clock controller consists of a clock generator, a timing generator, and a standby controller. XIN XOUT XTIN XTOUT 2.2.1 Clock Generator The clock ...
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High-frequency clock XIN XOUT XIN (a) Crystal/Ceramic (b) External oscillator resonator Figure 2-3 Examples of Resonator Connection Note:The function to monitor the basic clock directly at external is not provided for hardware, however, with dis- abling all interrupts and watchdog ...
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System Clock Controller 2.2.2 Timing Generator The timing generator generates the various system clocks supplied to the CPU core and peripheral hardware from the basic clock (fc or fs). The timing generator provides the following functions. 1. Generation of ...
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Timing Generator Control Register TBTCR (0036H) (DVOEN) (DVOCK) Selection of input to the 7th stage DV7CK of the divider Note 1: In single clock mode, do not set DV7CK to “1”. Note 2: Do not set “1” ...
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System Clock Controller (2) IDLE1 mode In this mode, the internal oscillation circuit remains active. The CPU and the watchdog timer are halted; however on-chip peripherals remain active (Operate using the high-frequency clock). IDLE1 mode is started by SYSCR2<IDLE> ...
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Switching back and forth between SLOW1 and SLOW2 modes are performed by SYSCR2<XEN>. In SLOW1 and SLEEP modes, the input clock to the 1st stage of the divider is stopped; output from the 1st to 6th stages is also stopped. ...
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System Clock Controller IDLE1 mode (a) Single-clock mode IDLE2 mode SLEEP2 mode SLEEP1 mode (b) Dual-clock mode Note 1: NORMAL1 and NORMAL2 modes are generically called NORMAL; SLOW1 and SLOW2 are called SLOW; IDLE0, IDLE1 and IDLE2 are called ...
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System Control Register 1 SYSCR1 (0038H) STOP RELM RETM OUTEN STOP STOP mode start Release method for STOP RELM mode Operating mode after STOP RETM mode OUTEN Port output during STOP mode Warm-up time at releasing WUT ...
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System Clock Controller 2.2.4 Operating Mode Control 2.2.4.1 STOP mode STOP mode is controlled by the system control register 1, the The pin is also used both as a port P20 and an STOP started by setting SYSCR1<STOP> to ...
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STOP pin XOUT pin NORMAL operation Confirm by program that the STOP pin input is low and start STOP mode. Figure 2-7 Level-sensitive Release Mode Note 1: Even if the STOP Note 2: In this case of changing to the ...
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System Clock Controller 3. When the warm-up time has elapsed, normal operation resumes with the instruction follow- Note 1: When the STOP mode is released, the start is made after the prescaler and the divider of the Note 2: ...
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Figure 2-9 STOP Mode Start/Release Page 19 TMP86C845UG ...
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System Clock Controller 2.2.4.2 IDLE1/2 mode and SLEEP1/2 mode IDLE1/2 and SLEEP1/2 modes are controlled by the system control register 2 (SYSCR2) and maskable interrupts. The following status is maintained during these modes. 1. Operation of the CPU and ...
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Start the IDLE1/2 and SLEEP1/2 modes After IMF is set to "0", set the individual interrupt enable flag (EF) which releases IDLE1/2 and SLEEP1/2 modes. To start IDLE1/2 and SLEEP1/2 modes, set SYSCR2<IDLE> to “1”. • Release the IDLE1/2 ...
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System Clock Controller Figure 2-11 IDLE1/2 and SLEEP1/2 Modes Start/Release Page 22 TMP86C845UG ...
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IDLE0 and SLEEP0 modes (IDLE0, SLEEP0) IDLE0 and SLEEP0 modes are controlled by the system control register 2 (SYSCR2) and the time base timer control register (TBTCR). The following status is maintained during IDLE0 and SLEEP0 modes. 1. Timing ...
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System Clock Controller • Start the IDLE0 and SLEEP0 modes • Release the IDLE0 and SLEEP0 modes of TBT and TBTCR<TBTEN>. cleared to “0” and the operation mode is returned to the mode preceding IDLE0 and SLEEP0 modes. Before ...
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Figure 2-13 IDLE0 and SLEEP0 Modes Start/Release Page 25 TMP86C845UG ...
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System Clock Controller 2.2.4.4 SLOW mode SLOW mode is controlled by the system control register 2 (SYSCR2). The following is the methods to switch the mode with the warm-up counter. (1) Switching from NORMAL2 mode to SLOW1 mode First, ...
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Switching from SLOW1 mode to NORMAL2 mode First, set SYSCR2<XEN> to turn on the high-frequency oscillation. When time for stabilization (Warm up) has been taken by the timer/counter (TC4,TC3), clear SYSCR2<SYSCK> to switch the main system clock to the ...
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System Clock Controller Figure 2-14 Switching between the NORMAL2 and SLOW Modes Page 28 TMP86C845UG ...
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Reset Circuit The TMP86C845UG has four types of reset generation procedures: An external reset input, an address trap reset, a watchdog timer reset and a system clock reset. Of these reset, the address trap reset, the watchdog timer and ...
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Reset Circuit 2.3.2 Address trap reset If the CPU should start looping for some cause such as noise and an attempt be made to fetch an instruction from the on-chip RAM (when WDTCR1<ATAS> is set to “1”) or the ...
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Page 31 TMP86C845UG ...
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Reset Circuit Page 32 TMP86C845UG ...
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Interrupt Control Circuit The TMP86C845UG has a total of 15 interrupt sources excluding reset, of which 2 source levels are multiplexed. Interrupts can be nested with priorities. Four of the internal interrupt sources are non-maskable while the rest are ...
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Interrupt enable register (EIR) Since interrupt latches can be read, the status for interrupt requests can be monitored by software. Note: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to ...
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Example 1 :Enables interrupts individually and sets IMF DI LDW : : EI Example 2 :C compiler description example unsigned int _io (3AH) EIRL; _DI(); EIRL = 10100000B; : _EI(); ← ; IMF 0 (EIRL), 1110100010100000B ; EF15 to EF13, ...
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Interrupt enable register (EIR) Interrupt Latches 15 14 ILH,ILL (003DH, 003CH) IL15 IL14 IL15 to IL2 Note 1: To clear any one of bits IL7 to IL4, be sure to write "1" into IL2 and IL3. Note 2: In ...
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Interrupt Source Selector (INTSEL) Each interrupt source that shares the interrupt source level with another interrupt source is allowed to enable the interrupt latch only when it is selected in the INTSEL register. The interrupt controller does not hold ...
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Interrupt Sequence 1-machine cycle Interrupt request Interrupt latch (IL) IMF Execute Execute instruction instruction a − Note 1: a: Return address entry address, b: Entry address, c: Address which RETI instruction is ...
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Using PUSH and POP instructions If only a specific register is saved or interrupts of the same source are nested, general-purpose registers can be saved/restored using the PUSH/POP instructions. Example :Save/store register using PUSH and POP instructions PINTxx: PUSH ...
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Interrupt Sequence Saving/Restoring general-purpose registers using PUSH/POP data transfer instruction Figure 3-4 Saving/Restoring General-purpose Registers under Interrupt Processing 3.4.3 Interrupt return Interrupt return instructions [RETI]/[RETN] perform as follows. As for address trap interrupt (INTATRAP required to alter ...
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Note recommended that stack pointer be return to rate before INTATRAP (Increment 3 times), if return inter- rupt instruction [RETN] is not utilized during interrupt service program under INTATRAP (such as Example 2). Note 2: When the ...
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External Interrupts Source Pin INT0 INT0 INT1 INT1 INT2 INT2 INT3 INT3 INT4 INT4 INT5 INT5 Note 1: In NORMAL1/2 or IDLE1/2 mode signal with no noise is input on an external interrupt pin, it takes a ...
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External Interrupt Control Register EINTCR (0037H) INT1NC INT0EN INT4ES INT1NC Noise reject time select INT0EN P00/ pin configuration INT0 INT4 ES INT4 edge select INT3 ES INT3 edge select INT2 ES INT2 edge select INT1 ES INT1 ...
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External Interrupts Page 44 TMP86C845UG ...
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Special Function Register (SFR) The TMP86C845UG adopts the memory mapped I/O system, and all peripheral control and data transfers are per- formed through the special function register (SFR). The SFR is mapped on address 0000H to 003FH. This chapter ...
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SFR Address 0028H 0029H 002AH 002BH 002CH 002DH 002EH 002FH 0030H 0031H 0032H 0033H 0034H 0035H 0036H 0037H 0038H 0039H 003AH 003BH 003CH 003DH 003EH 003FH Note 1: Do not access reserved areas by the program. Note 2: − ...
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I/O Ports The TMP86C845UG has 5 parallel input/output ports (35 pins) as follows. Primary Function Port P0 8-bit I/O port Port P1 8-bit I/O port Port P2 3-bit I/O port Port P3 8-bit I/O port Port P4 8-bit I/O ...
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Port P0 (P07 to P00) 5.1 Port P0 (P07 to P00) Port 8-bit input/output port which is also used as an external interrupt input, serial interface input/output and timer/counter input/output. When used as an input port ...
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Port P1 (P17 to P10) Port 8-bit input/output port which can be configured as an input or an output in one-bit unit under software control. Input/output mode is specified by the corresponding bit in the port ...
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Port P2 (P22 to P20) 5.3 Port P2 (P22 to P20) Port 3-bit input/output port also used as an external interrupt, a STOP mode release signal input, and low-frequency crystal oscillator con- nection pins. ...
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Port P3 (P37 to P30) Port 8-bit input/output port which can be configured as an input or an output in one-bit unit under software control. Port P3 is also used as an analog input. Input/output mode ...
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Port P4 (P47 to P40) 5.5 Port P4 (P47 to P40) Port 8-bit input/output port which can be configured as an input or an output in one-bit unit under software control. Input/output mode is specified by ...
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Time Base Timer (TBT) The time base timer generates time base for key scanning, dynamic displaying, etc. It also provides a time base timer interrupt (INTTBT). 6.1 Time Base Timer 6.1.1 Configuration MPX 23 15 fc/2 or fs/2 21 ...
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Time Base Timer Note 2: The interrupt frequency (TBTCK) must be selected with the time base timer disabled (TBTEN="0"). (The interrupt fre- quency must not be changed with the disable from the enable state.) Both frequency selection and enabling ...
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Divider Output ( DVO Approximately 50% duty pulse can be output using the divider output circuit, which is useful for piezoelectric buzzer drive. Divider output is from 6.2.1 Configuration Output latch D Q Data output MPX ...
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Divider Output (DVO) Example :1.95 kHz pulse output (fc = 16.0 MHz) Table 6-2 Divider Output Frequency ( Example : fc = 16.0 MHz 32.768 kHz ) DVOCK LD (TBTCR) , 00000000B LD (TBTCR) , 10000000B Divider ...
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Watchdog Timer (WDT) The watchdog timer is a fail-safe system to detect rapidly the CPU malfunctions such as endless loops due to spu- rious noises or the deadlock conditions, and return the CPU to a system recovery routine. The ...
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Watchdog Timer Control 7.2 Watchdog Timer Control The watchdog timer is controlled by the watchdog timer control registers (WDTCR1 and WDTCR2). The watch- dog timer is automatically enabled after the reset release. 7.2.1 Malfunction Detection Methods Using the Watchdog ...
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Watchdog Timer Control Register WDTCR1 (0034H) (ATAS) WDTEN Watchdog timer enable/disable Watchdog timer detection time WDTT [s] WDTOUT Watchdog timer output select Note 1: After clearing WDTOUT to “0”, the program cannot set it to “1”. ...
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Watchdog Timer Control 7.2.3 Watchdog Timer Disable To disable the watchdog timer, set the register in accordance with the following procedures. Setting the reg- ister in other procedures causes a malfunction of the microcontroller. 1. Set the interrupt master ...
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Watchdog Timer Reset When a binary-counter overflow occurs while WDTCR1<WDTOUT> is set to “1”, a watchdog timer reset request is generated. When a watchdog timer reset request is generated, the internal hardware is reset. The reset time is maximum ...
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Address Trap 7.3 Address Trap The Watchdog Timer Control Register 1 and 2 share the addresses with the control registers to generate address traps. Watchdog Timer Control Register WDTCR1 (0034H) Select address trap generation in ATAS ...
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Address Trap Reset While WDTCR1<ATOUT> is “1”, if the CPU should start looping for some cause such as noise and an attempt be made to fetch an instruction from the on-chip RAM (while WDTCR1<ATAS> is “1”) or the SFR ...
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Address Trap Page 64 TMP86C845UG ...
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TimerCounter (TC3, TC4) 8.1 Configuration 11 3 fc fc/2 16-bit mode G fc TC4 pin H S TC4M ...
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Configuration 8.2 TimerCounter Control The TimerCounter 3 is controlled by the TimerCounter 3 control register (TC3CR) and two 8-bit timer registers (TTREG3, PWREG3). TimerCounter 3 Timer Register TTREG3 7 6 (0018H) R/W PWREG3 7 6 (001AH) R/W Note 1: ...
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Note 7: The timer register settings are limited depending on the timer operating mode. For the detailed descriptions, see Table 8- 3. Note 8: The operating clock fc in the SLOW or SLEEP mode can be used only as the ...
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Configuration The TimerCounter 4 is controlled by the TimerCounter 4 control register (TC4CR) and two 8-bit timer registers (TTREG4 and PWREG4). TimerCounter 4 Timer Register TTREG4 7 6 (0019H) R/W PWREG4 7 6 (001BH) R/W Note 1: Do not ...
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Note 6: To the TimerCounter in the 16-bit mode, select the source clock by programming TC3CR<TC3CK>. Set the timer start control and timer F/F control by programming TC4S and TFF4, respectively. Note 7: The operating clock settings are limited depending ...
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Configuration Table 8-3 Constraints on Register Values Being Compared Operating mode 8-bit timer/event counter 8-bit PDO 8-bit PWM 16-bit timer/event counter Warm-up counter 16-bit PWM 16-bit PPG Note Register Value 1≤ (TTREGn) ≤255 1≤ ...
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Function The TimerCounter 3 and 4 have the 8-bit timer, 8-bit event counter, 8-bit programmable divider output (PDO), 8- bit pulse width modulation (PWM) output modes. The TimerCounter 3 and 4 (TC3, 4) are cascadable to form a 16- ...
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Configuration TC4CR<TC4S> Internal Source Clock Counter TTREG4 ? INTTC4 interrupt request 8.3.2 8-Bit Event Counter Mode (TC3 the 8-bit event counter mode, the up-counter counts up at the falling edge of the input pulse to the TCj ...
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Example :Generating 1024 Hz pulse using TC4 (fc = 16.0 MHz Note 1: In the programmable divider output mode, do not change the TTREGj setting while the timer is running. Since TTREGj is not in the shift ...
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Configuration Figure 8-4 8-Bit PDO Mode Timing Chart (TC4) Page 74 TMP86C845UG ...
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Pulse Width Modulation (PWM) Output Mode (TC3, 4) This mode is used to generate a pulse-width modulated (PWM) signals with bits of resolution. The up-counter counts up using the internal clock. When a match between ...
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Configuration Figure 8-5 8-Bit PWM Mode Timing Chart (TC4) Page 76 TMP86C845UG ...
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Timer Mode (TC3 and 4) In the timer mode, the up-counter counts up using the internal clock. The TimerCounter 3 and 4 are cascad- able to form a 16-bit timer. When a match between the up-counter and the ...
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Configuration 8.3.6 16-Bit Event Counter Mode (TC3 and 4) In the event counter mode, the up-counter counts up at the falling edge to the TC3 pin. The TimerCounter 3 and 4 are cascadable to form a 16-bit event counter. ...
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CLR (TC4CR).3: Stops the timer. CLR (TC4CR).7 : Sets the Note 3: To enter the STOP mode, stop the timer and then enter the STOP mode. If the STOP mode is entered with- out stopping of the timer when fc, ...
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Configuration Figure 8-7 16-Bit PWM Mode Timing Chart (TC3 and TC4) Page 80 TMP86C845UG ...
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Programmable Pulse Generate (PPG) Output Mode (TC3 and 4) This mode is used to generate pulses with up to 16-bits of resolution. The timer counter 3 and 4 are cascad- able to enter the 16-bit PPG mode. The ...
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Configuration Figure 8-8 16-Bit PPG Mode Timing Chart (TC3 and TC40) Page 82 TMP86C845UG ...
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Warm-Up Counter Mode In this mode, the warm-up period time is obtained to assure oscillation stability when the system clocking is switched between the high-frequency and low-frequency. The timer counter 3 and 4 are cascadable to form a 16-bit ...
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Configuration 8.3.9.2 High-Frequency Warm-Up Counter Mode (SLOW1 → SLOW2 → NORMAL2 → NORMAL1) In this mode, the warm-up period time from a stop of the high-frequency clock fc to the oscillation sta- bility is obtained. Before starting the timer, ...
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Synchronous Serial Interface (SIO) The serial interfaces connect to an external device via SI, SO, and When these pins are used as serial interface, the output latches for each port should be set to "1". 9.1 Configuration Internal data ...
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Control 9.2 Control The SIO is controlled using the serial interface control register (SIOCR1). The operating status of the serial inter- face can be inspected by reading the status register (SIOCR1). Serial Interface Control Register SIOCR1 7 6 (0026H) ...
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Serial Interface Status Register SIOSR (0027H) SIOF SEF TXF Serial transfer operation status SIOF monitor SEF Number of clocks monitor TXF Transmit buffer empty flag RXF Receive buffer full flag TXERR Transfer operation error flag RXERR Receive ...
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Function 9.3 Function 9.3.1 Serial clock 9.3.1.1 Clock source The serial clock can be selected by using SIOCR1<SCK>. When the serial clock is changed, the writing instruction to SIOCR1<SCK> should be executed while the transfer is stopped (when SIOSR<SIOF> ...
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External clock When an external clock is selected by setting SIOCR1<SCK> to “111B”, the clock via the from an external source is used as the serial clock. To ensure shift operation, the serial clock pulse width must be 4/fc ...
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Function 9.3.2 Transfer bit direction Transfer data direction can be selected by using SIOCR1<SIODIR>. The transfer data direction can't be set individually for transmit and receive operations. When the data direction is changed, the writing instruction to SIOCR1<SIODIR> should ...
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LSB receive mode LSB receive mode is selected by setting SIOCR1<SIODIR> to “1”, in which case the data is received sequentially beginning with the least significant bit (Bit0). 9.3.2.3 Transmit/receive mode (1) MSB transmit/receive mode MSB transmit/receive mode are ...
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Function (2) During the transmit operation When data is written to SIOTDB, SIOSR<TXF> is cleared to “0”. In internal clock operation, in case a next transmit data is not written to SIOTDB, the serial clock stops to “H” level ...
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SIOCR1<SIOS> SIOSR<SIOF> Start shift operation SIOSR<SEF> pin SCK SO pin SIOSR<TXF> INTSIO interrupt request SIOTDB <SIOS> ...
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Function SIOCR1<SIOS> SIOSR<SIOF> SIOSR<SEF> pin SCK SO pin SIOSR<TXF> SIOSR<TXERR> INTSIO interrupt request SIOTDB A Writing transmit SIOCR1 data A <SIOINH> Figure 9-9 Example of Transmit Error Processingme 9.3.3.2 Receive mode The receive mode is selected by writing “01B” ...
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If received data is not read out from SIORDB receive error occurs immediately after shift opera- tion is finished. Then INTSIO interrupt request is generated after SIOSR<RXERR> is set to “1”. (3) Stopping the receive operation There are two ways ...
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Function SIOCR1<SIOS> SIOSR<SIOF> SIOSR<SEF> pin SCK SI pin SIOSR<RXF> INTSIO interrupt request SIORDB Figure 9-11 Example of External Clock and MSB Receive Mode (4) Receive error processing Receive errors occur on the following situation. To protect SIORDB and the ...
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SIOCR1<SIOS> SIOSR<SIOF> Start shift operation SIOSR<SEF> pin SCK SI pin SIOSR<RXF> SIOSR<RXERR> INTSIO interrupt request SIORDB ...
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Function (2) During the transmit/receive operation When data is written to SIOTDB, SIOSR<TXF> is cleared to “0” and when a data is read from SIORDB, SIOSR<RXF> is cleared to “0”. In internal clock operation, in case of the condition ...
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SIOCR1<SIOS> SIOSR<SIOF> Start shift operation SIOSR<SEF> pin output SCK SO pin pin INTSIO interrupt request SIOSR<TXF> SIOTDB A Writing transmit data A SIOSR<RXF> SIORDB Figure ...
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Function SIOCR1<SIOS> SIOSR<SIOF> SIOSR<SEF> pin output SCK SO pin SI pin INTSIO interrupt request SIOSR<TXF> SIOTDB A Writing transmit data A SIOSR<RXF> SIORDB Figure 9-14 Example of External Clock and MSB Transmit/Receive Mode (4) Transmit/receive error processing Transmit/receive errors ...
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SIOCR1<SIOS> SIOSR<SIOF> Start shift operation SIOSR<SEF> pin output SCK SO pin pin ...
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Function SIOCR1<SIOS> SIOSR<SIOF> SIOSR<SEF> pin output SCK SO pin SI pin INTSIO interrupt request SIOSR<TXF> SIOTDB A Writing transmit data A SIOSR<RXF> SIOSR<RXERR> SIORDB SIOCR1<SIOINH> Figure 9-16 Example of Transmit/Receive (Receive) Error Processing pin SCK SIOSR<SIOF> SO pin Figure ...
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AD Converter (ADC) The TMP86C845UG have a 10-bit successive approximation type AD converter. 10.1 Configuration The circuit configuration of the 10-bit AD converter is shown in Figure 10-1. It consists of control register ADCCR1 and ADCCR2, converted value ...
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Register configuration 10.2 Register configuration The AD converter consists of the following four registers converter control register 1 (ADCCR1) This register selects the analog channels and operation mode (Software start or repeat) in which to per- form ...
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AD Converter Control Register ADCCR2 (001DH) IREFON DA converter (Ladder resistor) connection IREFON control AD conversion time select ACK (Refer to the following table about the con- version time) Note 1: Always set bit0 in ADCCR2 ...
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Register configuration EOCF ADBF Note 1: The ADCDR2<EOCF> is cleared to "0" when reading the ADCDR1. Therfore, the AD conversion result should be read to ADCDR2 more first than ADCDR1. Note 2: The ADCDR2<ADBF> is set to "1" when ...
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Function 10.3.1 Software Start Mode After setting ADCCR1<AMD> to “01” (software start mode), set ADCCR1<ADRS> to “1”. AD conver- sion of the voltage at the analog input pin specified by ADCCR1<SAIN> is thereby started. After completion of the AD ...
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Function ADCCR1<AMD> AD conversion start ADCCR1<ADRS> Conversion operation Indeterminate ADCDR1,ADCDR2 ADCDR2<EOCF> INTADC interrupt request ADCDR1 ADCDR2 10.3.3 Register Setting 1. Set up the AD converter control register 1 (ADCCR1) as follows: • Choose the channel to AD convert using ...
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Example :After selecting the conversion time 19.5 µ MHz and the analog input channel AIN3 pin, perform AD con- version once. After checking EOCF, read the converted value, store the lower 2 bits in address 0009EH nd store ...
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Analog Input Voltage and AD Conversion Result 10.5 Analog Input Voltage and AD Conversion Result The analog input voltage is corresponded to the 10-bit digital value converted by the AD as shown in Figure 10-4. 3FF H 3FE H ...
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... The internal equivalent circuit of the analog input pins is shown in Figure 10-5. The higher the output impedance of the analog input source, more easily they are susceptible to noise. Therefore, make sure the out- put impedance of the signal source in your design is 5 kΩ or less. Toshiba also recommends attaching a capac- itor external to the chip. ...
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Precautions about AD Converter Page 112 TMP86C845UG ...
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Input/Output Circuitry 11.1 Control Pins The input/output circuitries of the TMP86C845UG control pins are shown below. Control Pin I/O XIN Input XOUT Output Osc. enable XTIN Input XTOUT Output Input RESET Output TEST Input Note 1: The TEST pin ...
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Input/Output Ports 11.2 Input/Output Ports Port I/O P07 to P05 I/O P00 P04 to P01 I/O P15 I/O P12 to P10 P17, P16 I/O P14, P13 P2 I/O Note: In TMP86PM47/PH47, P04 to P01, P17, 16, P14 and P13 ...
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Port I/O Initial "High-Z" Data output P3 I/O Disable Pin input Initial "High-Z" Data output P4 I/O Disable Pin input Input/Output Circuitry VDD R VDD R Page 115 TMP86C845UG Remarks Tri-state I 100 Ω (typ.) Tri-state I/O High ...
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Input/Output Ports Page 116 TMP86C845UG ...
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Electrical Characteristics 12.1 Absolute Maximum Ratings The absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any absolute maximum rating is ...
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DC Characteristics 12.3 DC Characteristics Parameter Symbol V Hysteresis voltage HS I IN1 I Input current IN2 I IN3 R IN1 Input resistance R IN2 I Output leakage LO1 current I LO2 V Output high voltage ...
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AD Conversion Characteristics Parameter Symbol Analog reference voltage Power supply voltage of analog control circuit ∆V Analog reference voltage range Analog input voltage Power supply current of analog refer- ence Voltage Non linearity error Zero point error Full scale ...
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... Note 2: For the resonators to be used with Toshiba microcontrollers, we recommend ceramic resonators manufactured by Murata Manufacturing Co., Ltd. For details, please visit the website of Murata at the following URL: http://www ...
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Handling Precaution - The solderability test conditions for lead-free products (indicated by the suffix G in product name) are shown below. 1. When using the Sn-37Pb solder bath Solder bath temperature = 230 °C Dipping time = 5 seconds ...
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Recommended Oscillating Conditions Page 122 TMP86C845UG ...
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Package Dimension P-LQFP44-1010-0.80A Page 123 TMP86C845UG Unit: mm ...
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Page 124 TMP86C845UG ...
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... This is a technical document that describes the operating functions and electrical specifications of the 8-bit microcontroller series TLCS-870/C (LSI). Toshiba provides a variety of development tools and basic software to enable efficient software development. These development tools have specifications that support advances in microcomputer hardware (LSI) and can be used extensively ...
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