PD45128168G5-A75A-9JF Elpida Memory, Inc., PD45128168G5-A75A-9JF Datasheet - Page 29

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PD45128168G5-A75A-9JF

Manufacturer Part Number
PD45128168G5-A75A-9JF
Description
128M-bit synchronous DRAM 4-bank, LVTTL MOS integrated circuit
Manufacturer
Elpida Memory, Inc.
Datasheet
11.3 Write to Read Command Interval
/CAS latency = 2
/CAS latency = 3
Write command and Read command interval is also 1 cycle.
Only the write data before Read command will be written.
The data bus must be Hi-Z at least one cycle prior to the first D
Command
Command
CLK
DQ
DQ
T0
WRITE A
WRITE A
DA1
DA1
T1
READ B
READ B
T2
Hi-Z
Hi-Z
Data Sheet E0031N30
T3
QB1
OUT
T4
PD45128441, 45128841, 45128163
.
QB2
QB1
T5
QB3
QB2
T6
QB4
QB3
T7
Burst length = 4
QB4
T8
29

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