PD45128168G5-A75A-9JF Elpida Memory, Inc., PD45128168G5-A75A-9JF Datasheet - Page 8

• Manufacturer Part Number: PD45128168G5-A75A-9JF
• Description: 128M-bit synchronous DRAM 4-bank, LVTTL MOS integrated circuit
• Manufacturer: Elpida Memory, Inc.

1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Auto Precharge ............................................................................................................................... 26
11. Read / Write Command Interval .................................................................................................... 28
12. Burst Termination .......................................................................................................................... 31
8
Input / Output Pin Function ........................................................................................................... 10
Commands ...................................................................................................................................... 11
Simplified State Diagram ............................................................................................................... 14
Truth Table ...................................................................................................................................... 15
4.1 Command Truth Table ............................................................................................................................ 15
4.2 DQM Truth Table ..................................................................................................................................... 15
4.3 CKE Truth Table ...................................................................................................................................... 15
4.4 Operative Command Table .................................................................................................................... 16
4.5 Command Truth Table for CKE ............................................................................................................. 19
Initialization .................................................................................................................................... 20
Programming the Mode Register ................................................................................................. 21
Mode Register ................................................................................................................................ 22
7.1 Burst Length and Sequence .................................................................................................................. 23
Address Bits of Bank-Select and Precharge ............................................................................... 24
Precharge ........................................................................................................................................ 25
10.1
10.2
11.1
11.2
11.3
11.4
12.1
12.2
Read with Auto Precharge .................................................................................................................. 26
Write with Auto Precharge .................................................................................................................. 27
Read to Read Command Interval ....................................................................................................... 28
Write to Write Command Interval ....................................................................................................... 28
Write to Read Command Interval ....................................................................................................... 29
Read to Write Command Interval ....................................................................................................... 30
Burst Stop Command .......................................................................................................................... 31
Precharge Termination ....................................................................................................................... 32
12.2.1
12.2.2
Precharge Termination in READ Cycle ................................................................................... 32
Precharge Termination in WRITE Cycle ................................................................................. 33
Data Sheet E0031N30
CONTENTS
PD45128441, 45128841, 45128163