PD45128168G5-A75A-9JF Elpida Memory, Inc., PD45128168G5-A75A-9JF Datasheet - Page 31

• Manufacturer Part Number: PD45128168G5-A75A-9JF
• Description: 128M-bit synchronous DRAM 4-bank, LVTTL MOS integrated circuit
• Manufacturer: Elpida Memory, Inc.

12. Burst Termination
burst stop command and the other is the precharge command.
12.1 Burst Stop Command
goes to Hi-Z after the /CAS latency from the burst stop command.
Remark BST: Burst stop command
to Hi-Z at the same clock with the burst stop command.
Remark BST: Burst stop command
There are two methods to terminate a burst operation other than using a Read or a Write command. One is the
During a read cycle, when the burst stop command is issued, the burst read data are terminated and the data bus
During a write cycle, when the burst stop command is issued, the burst write data are terminated and data bus goes
/CAS latency = 2, 3
/CAS latency = 2
/CAS latency = 3
Command
Command
CLK
DQ
DQ
CLK
DQ
T0
T0
READ
WRITE
T1
D1
T1
T2
D2
Data Sheet E0031N30
T2
Q1
T3
D3
T3
BST
Q1
PD45128441, 45128841, 45128163
Q2
T4
D4
T4
Q3
Q2
BST
T5
T5
Q3
T6
T6
Hi-Z
Burst length = X
Burst length = X
T7
T7
Hi-Z
Hi-Z
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