PD45128168G5-A75A-9JF Elpida Memory, Inc., PD45128168G5-A75A-9JF Datasheet - Page 32

• Manufacturer Part Number: PD45128168G5-A75A-9JF
• Description: 128M-bit synchronous DRAM 4-bank, LVTTL MOS integrated circuit
• Manufacturer: Elpida Memory, Inc.

12.2 Precharge Termination
12.2.1 Precharge Termination in READ Cycle
When /CAS latency is 3, the read data will remain valid until two clocks after the precharge command.
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During a read cycle, the burst read operation is terminated by a precharge command.
When the precharge command is issued, the burst read operation is terminated and precharge starts.
The same bank can be activated again after t
To issue a precharge command, t
When /CAS latency is 2, the read data will remain valid until one clock after the precharge command.
Command
CLK
DQ
Command
CLK
DQ
T0
T0
READ
T1
RAS
READ
T1
must be satisfied.
T2
RP
T2
from the precharge command.
Data Sheet E0031N30
T3
Q1
T3
Q1
T4
Q2
T4
PD45128441, 45128841, 45128163
PRE
Q2
T5
PRE
Burst length = X, /CAS latency = 2
Q3
T5
Burst length = X, /CAS latency = 3
Q3
T6
(t
Q4
t
RAS
RP
T6
t
RP
must be satisfied)
(t
Q4
RAS
T7
ACT
must be satisfied)
T7
Hi-Z
ACT
T8
Hi-Z