STG3000X STMicroelectronics, STG3000X Datasheet - Page 40

• Manufacturer Part Number: STG3000X
• Description: 128-BIT 3D MULTIMEDIA ACCELERATOR
• Manufacturer: STMicroelectronics

RIVA 128
8.2
The Media Port transfers data using a Polling Pro-
tocol. The Media Port is enabled on the RIVA 128
by the host system software. The first cycle after
being enabled is a Poll Cycle. The MPC ASIC
must respond to every poll cycle with valid data
during DTACK active. If no transactions are need-
ed, it responds with 00h. The Media Port will con-
tinue to Poll until a transaction is requested, or un-
til there is a Host CPU access to an external reg-
ister.
Polling Cycle
Media Port initiates a Polling Cycle whenever
there is no pending transaction. This gives the
MPC ASIC a mechanism to initiate a transaction.
The valid Polling commands are listed in the Poll-
ing Command table. The priority for the polling re-
quests should be to give the Display Data FIFO
highest priority.
CPU Register Write
Initiated by the Host system software.
CPU Register Read Issue
Initiated by the Host system software. The read
differs from the write in the fact that it must be done
in two separate transfers. The Read Issue is just
Table 9. Media Port Transactions
Table 10. Polling Cycle Commands
40/77
11xx0000
00xx----
01xx1111
11xx1111
01xx0001
11xx1000
BIT
0
1
3
4
BI-DIRECTIONAL MEDIA PORT POLLING
COMMANDS USING MPC
A0 Cycle
00000000
000xxxx1
000xxx1x
000x1xxx
0001xxxx
Data
Poll_Cycle
CPUWrite
CPURead_Issue
CPURead_Receive
VCD_DMA_Write
Display_Data_Read
NV_PME_VMI_POLL_UNCD
NV_PME_VMI_POLL_VIDCD
NV_PME_VMI_POLL_INT
NV_PME_VMI_POLL_CPURDREC
NULL
Transaction
128-BIT 3D MULTIMEDIA ACCELERATOR
the initiation of the read cycle. The Media Port
transfers the address of the register to be read
during this cycle. After completion of the Read Is-
sue cycle the media port goes back to polling for
the next transaction. When it receives a Read
Data ready command, it will start the next cycle in
the read.
CPU Register Read Receive
Initiated by the MPC ASIC when it has read data
ready to be transferred to the media port. The
MPC ASIC waits for the next polling cycle and re-
turns a Read Data Ready status. The media port
will transfer the read data on the next Read Re-
ceive Cycle. The PCI bus will be held off and retry
until the register read is complete.
Video Compressed Data DMA Write
Initiated by the MPC ASIC with the appropriate
Polling Command. The media port manages the
Video Compressed data buffer in system memory.
Each request for data will return 32 bytes in a sin-
gle burst.
Display Data DMA Read
Initiated by the MPC ASIC with the polling com-
mand. The MPC ASIC initiates this transfer when
it wishes to transfer video data in ITU-R-656 for-
mat.
Polling Cycle
CPU Register Write
CPU Register Read Issue
CPU Register Read Receive
Video Compressed Data DMA Write
Display Data DMA Read
Request DMA Read of Display Data
Request DMA Write of Video Compressed Data
Request for Interrupt
Respond to Read Issue - Read Data Ready
No Transactions requested
Description
Description