STG3000X STMicroelectronics, STG3000X Datasheet - Page 49

• Manufacturer Part Number: STG3000X
• Description: 128-BIT 3D MULTIMEDIA ACCELERATOR
• Manufacturer: STMicroelectronics

128-BIT 3D MULTIMEDIA ACCELERATOR
10
The RIVA 128 latches its configuration on the trail-
ing edge of RST# and holds its system bus inter-
face in a high impedance state until this time. To
accomplish this, pull-up or pull-down resistors are
connected to the FBA[9:0] pins as appropriate.
Power-on reset FBA[9:0] bit assignments
[9]
[8:7]
[6]
[5]
[4]
[3:2]
[1]
[0]
POWER-ON RESET CONFIGURATION
PCI Mode. This bit indicates whether the RIVA 128 initializes with PCI 2.1 compliance
0 = RIVA 128 is PCI 2.0 compliant (does not support delayed transactions)
1 = RIVA 128 is PCI 2.1 compliant (supports 16 clock target latency requirement).
TV Mode. These bits select the timing format when TV mode is enabled.
00 = Reserved
01 = NTSC
10 = PAL
11 = TV mode disabled
Crystal Frequency. This bit should match the frequency of the crystal or reference clock connect-
ed to XTALOUT and XTALIN.
0 = 13.500MHz (used where TV output may be enabled)
1 = 14.31818MHz
Host Interface
0 = PCI
1 = AGP (Bit 0 must also be pulled high to indicate 66MHz)
RAM Width
0 = 64-bit framebuffer data bus width (the upper 64-bit data bus and byte selects are tri-state)
1 = 128-bit framebuffer data bus width
RAM Type
00 = Reserved
01 = 8Mbit SDRAM or SGRAM organized as 128K x 2 banks x 32-bit (normal SGRAM mode).
10 = Reserved
11 = 8Mbit SDRAM or SGRAM organized as 128K x 2 banks x 32-bit, framebuffer I/O pins remain
tri-stated after reset.
Sub-Vendor. This bit indicates whether the PCI Subsystem Vendor field is located in the system
motherboard BIOS or adapter card VGA BIOS. If the Subsystem Vendor field is located in the sys-
tem BIOS it must be written by the system BIOS to the PCI configuration space prior to running
any PnP code.
0 = System BIOS (Subsystem Vendor ID and Subsystem ID set to 0x0000)
1 = Adapter card VGA BIOS (Subsystem Vendor ID and Subsystem ID read from ROM BIOS at
location 0x54 - 0x57)
Bus Speed. This bit indicates the value returned in the 66MHZ bit in the PCI Configuration regis-
ters (see page 64).
0 = RIVA 128 PCI interface is 33MHz
1 = RIVA 128 is 66MHz capable
Mode
PCI
9
8
TV Mode
7
Crystal
6
Interface
Host
5
Since there are no internal pull-up or pull-down re-
sistors and the data bus should be floating during
reset, a resistor value of 47K
cient.
Width
RAM
4
3
RAM Type
2
Vendor
Sub-
should be suffi-
1
RIVA 128
Speed
Bus
0
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