STG3000X STMicroelectronics, STG3000X Datasheet - Page 64

• Manufacturer Part Number: STG3000X
• Description: 128-BIT 3D MULTIMEDIA ACCELERATOR
• Manufacturer: STMicroelectronics

RIVA 128
Byte offsets 0x07 - 0x04
64/77
Device Status Register (0x07 - 0x06)
Command Register (0x05 - 0x04)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
26:25
24:22
19:16
15:9
Bits
Bits
31
30
29
28
27
21
20
0x07
Function
Reserved
SERR_SIGNALLED is set whenever the RIVA 128 asserts SERR#.
RECEIVED_MASTER indicates that a master device's transaction (except for
Special Cycle) was terminated with a master-abort. This bit is clearable (=1).
0=No abort
1=Master aborted
RECEIVED_TARGET indicates that a master device's transaction was termi-
nated with a target-abort. This bit is clearable (=1).
0=No abort
1=Master received target aborted
Reserved
The DEVSEL_TIMING bits indicate the timing of DEVSEL#. These bits indi-
cate the slowest time that the RIVA 128 asserts DEVSEL# for any bus com-
mand except Configuration Read and Configuration Write. The RIVA 128
responds with medium DEVSEL# for VGA, memory and I/O accesses. For
accesses to the 16MByte memory ranges described by the BARs, the chip
responds with fast decode (no wait states).
00=fast
01=medium
Reserved
66MHZ indicates that the RIVA 128 is capable of 66MHz operation. This bit
reflects the latched state of the 66MHz/33MHz strap option.
CAP_LIST indicates that there is a linked list of registers containing informa-
tion about new capabilities not available within the original PCI configuration
structure. This bit indicates that the (byte) Capability Pointer Register located
at 0x34 points to the start of this linked list.
Reserved
Function
Reserved
0x06
128-BIT 3D MULTIMEDIA ACCELERATOR
0x05
9
8
7
6
5
0x04
4
3
R W 0
R W 0
R W 0
R W I
R W I
R - 0
R - 0
R - 1
R - 0
R - 1
R - 1
R - 0
R - 0
2
1
0