PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 404

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Register 0774H: TXSDQ FIFO EOP Error Port and Interrupt Indication
EOPI
EOP_FIFO[5:0]
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
This bit is set when two EOPs arrive consecutively on the FIFO without being separated by a
SOP. If WCIMODE is set to logic 1, only over-writing with a ‘1’ clears this bit. If
WCIMODE is set to logic 0, then a read of this register automatically clears the bit.
These bits are used to indicate the FIFO identity. This field should contain the value
“000000”. Otherwise a system error should be declared. These bits are valid only when the
interrupt bit is logic 1.
R
R
R
R
Type
R
R
R
Unused
Unused
EOP_FIFO[5]
EOP_FIFO[4]
EOP_FIFO[3]
EOP_FIFO[2]
EOP_FIFO[1]
EOP_FIFO[0]
EOPI
Function
Unused
Unused
Unused
Unused
Unused
Unused
Unused
S/UNI-2488 Telecom Standard Product Datasheet
Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Released
404