PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 552
PM5381-BI
Manufacturer Part Number
PM5381-BI
Description
ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
Manufacturer
PMC-Sierra, Inc.
Datasheet
1.PM5381-BI.pdf
(586 pages)
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14.1
14.2
14
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
APSI_P[X]/APSI_N[X]
APSI_P[Y]/APSI_N[Y]
Functional Timing
Incoming APS Serial TelecomBus
Figure 37 shows the relative timing of the incoming APS serial TelecomBus LVDS links. Links
carry SONET/SDH frame octets that are encoded in 8B/10B characters. Frame boundaries,
justification events and alarm conditions are encoded in special control characters. The upstream
devices sourcing the links share a common clock and have a common transport frame alignment
that is synchronized by the APS Input Frame Pulse signal (APSIFP). Due to phase noise of clock
multiplication circuits and backplane routing discrepancies, the links will not phase aligned to
each other but are frequency locked. The delay from APSIFP being sampled high to the first and
last J0 character is shown in Figure 37. In this example, the first J0 is delivered by one of the
four APSI links (APSI+/APSI-). The delay to the last J0 represents the time when the all the links
have delivered their J0 character. In the example below, one of the links (APSI+[Y]/APSI-[Y]) is
shown to be the slowest. The minimum value for the internal programmable delay
(AIJ0DLY[13:0]) is the delay to the last J0 character plus 15. The maximum value is the delay to
the first J0 character plus 31. Consequently, the external system must ensure that the relative
delays between all the APSI LVDS links be less than 16 characters (approximately 205ns). The
relative phases of the links in Figure 37 are shown for illustrative purposes only.
Figure 37 Incoming APS Serial TelecomBus Timing
Outgoing APS Serial TelecomBus
Figure 38 shows the timing relationships around the APSIFP signal. The Outgoing APS J0 Frame
Pulse (APSOFP) signal indicates the approximate time at which the J0 byte is available on the
output APS LVDS links. Note the time between APSIFP and APSOFP is approximately 22
APSIFPCLK cycles.
APSIFPCLK
APSIFP
1
2
3
Delay to First J0
Delay to First J0
4
A2
Delay to Last J0
Delay to Last J0
A2
5
S/UNI-2488 Telecom Standard Product Datasheet
A2
A2
6
J0
A 2
7
Z0
A2
8
Z0
J0
9
Z0
Z0
10
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