PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 5

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Issue
No.
Issue 3
Issue
Date
April
2002
Details of Change
Change TRSTB pin description to “TRSTB must be asserted at some
point after power up and before the device registers are accessed.”
Added pull-up resistance on input pads with pull-ups (30 to 50 kOhm).
Modified device ID for rev D in register 0x0000 and JTAG description.
Modified RCA pin description to remove erroneous info regarding early
deassertion of RCA (4 or 0 bytes available in FIFO).
Corrected RVAL description.
Corrected TCA description.
Updated limit for maximum allowable skew between APS links in
Section 14.1, Incoming APS Serial TelecomBus.
Updated functional timing diagrams for APSI and APSO links in Section
14.1, Incoming APS Serial TelecomBus, and 14.2, Outgoing APS Serial
TelecomBus.
Changed default state of TRAIN, DOOLV, and ROOLV in register
0x0013 to ‘X’.
Modified RPAISINS_EN register bit description in register 0x0902 to
indicate PAIS can be asserted on detection of LAIS, PAIS, or LOP
using this register bit.
Added to RHPP’s status bits (NEWPTR, ILLJREQ, PAISV, PLOPV,
NDF, INVNDF, DISCOPA) to indicate they are only valid for master
timeslots.
Changed ILLPTR register bit to Unused. in register RHPP Indirect
Register 5.
Modified INVCNT description to state it must be set to logic 1 for
SONET compliant behaviour.
Bit 3 of register 0x780 must be set to logic 1 to improve PL3 output
propagation time to meet timing specification.
Modified C0_CRU/C1_CRU and C0_CSU/C1_CSU pin description to
state that external capacitors are required in all configurations.
Document issued for Revision C of the device.
Filled out the Loopback description in the Operations Section.
Updated mechanical diagram.
Added 2.488Gb/s output jitter specs.
Added new registers 0x0900 to 0x90F.
Changed device ID code in JTAG and in register 0 for rev C.
Added AC Timing for SONET Overhead signals.
Added typical AC timing.
Reduced the Tx ECL/PECL output levels to match the new 2.5G
transmitter.
Added statement to recommend setting CSU_MODE[2] register bit in
register 0x0021 to logic 1 for optimal non-loop-timed intrinsic jitter
performance.
S/UNI-2488 Telecom Standard Product Datasheet
Released
5