PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 537

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

13.15.2 Error Detection and Accumulation
13.16 Using the SONET/SDH Bit Error Rate Alarm Monitor (SBER)
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Upon detecting 3 consecutive PRBS byte errors, the monitor will enter the Out of
Synchronization State and automatically try to resynchronize to the incoming PRBS stream.
Once synchronized to the incoming stream, it will take 4 consecutive non-erroneous PRBS bytes
to change back into the Synchronized State. The auto synchronization is useful when the input
frame alignment of the monitored stream changes. The realignment will affect the PRBS
sequence causing all input PRBS bytes to mismatch and forcing the need for a resynchronization
of the monitor. The auto resynchronization does this, detecting a burst of errors and
automatically re-synchronizing.
By comparing the received PRBS byte with the calculated PRBS byte, the monitor is able to
detect byte errors in the payload. A byte error is detected on a comparison mismatch of the two
bytes. Only a single byte error is counted regardless of the number of erroneous bits in the byte.
All byte errors are accumulated in a 16 bit byte error counter. The error counter will saturate at its
maximum value of FFFFh, ie it will not wrap around to 0000h if further PRBS byte errors are
encountered. The counter is readable via the PRGM Monitor Error Count. An indirect read to that
register will initiate a transfer of the error counter into the registers for reading. The error counter
is cleared when transferred into the registers and the accumulation restarts at zero. All 48 STS-1
error counts belonging to the concatenated stream must be read. The error counts in each
associated register must be summed by software.
Bit errors are accumulated only when the monitor is in synchronized state. To enter the
synchronize state, the monitor must have synchronized to the incoming PRBS stream and
received 4 consecutive bytes without errors. Once synchronized, the monitor falls out of
synchronization when forced to by programming high the RESYNC register bit, or once it detects
3 consecutive PRBS byte errors. When out of synchronization, detected errors are not
accumulated. However, it should be noted that when the PRGM goes out of synchronization, 1
or 2 extra errors may be counted. In other words, the 3 errors which cause the PRGM to lose
synch may in fact be counted as 3, 4, or 5 errors.
Refer to PMC’s application note PMC-1950820 “SONET/SDH Bit error Threshold Monitoring”
for further details on SONET/SDH bit-error threshold requirements. Table 26 and Table 27 show
the set-up configuration to meet the SONET and SDH bit-error rate monitor thresholds.
Table 26 BERM Configuration for SDH STM-16c
BER
1.0e-3
1.0e-4
1.0e-5
1.0e-6
1.0e-7
1.0e-8
Evaluation
Period
0.01
0.1
1
10
100
1000
0
CMODE
0
0
0
0
0
Accumulation
Period
00000A
000064
0003E8
002710
0186A0
0F4240
S/UNI-2488 Telecom Standard Product Datasheet
Detection
Threshold
2AF8
2AF8
2AF8
2AF8
2AF8
2AF8
Clear
Threshold
A28
A28
A28
A28
A28
A28
Released
537