LPC1769 NXP Semiconductors, LPC1769 Datasheet
LPC1769
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LPC1769 Summary of contents
Page 1
... The ARM Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branching. The peripheral complement of the LPC1769/68/67/66/65/64 includes up to 512 kB of flash memory data memory, Ethernet MAC, USB Device/Host/OTG interface, 8-channel general purpose DMA controller, 4 UARTs, 2 CAN channels, 2 SSP controllers, ...
Page 2
... Ethernet MAC with RMII interface and dedicated DMA controller (LPC1769/68/67/66/64 only). USB 2.0 full-speed device/Host/OTG controller with dedicated DMA controller and on-chip PHY for device, Host, and OTG functions (LPC1769/68/66/65 only). The LPC1764 includes a device controller only. Four UARTs with fractional baud rate generation, internal FIFO, and DMA support. ...
Page 3
... Code Read Protection (CRP) with different security levels. Unique device serial number for identification purposes. Available as 100-pin LQFP package (14 mm × × 1.4 mm). LPC1769_68_67_66_65_64_4 Product data sheet LPC1769/68/67/66/65/64 32-bit ARM Cortex-M3 microcontroller Rev. 04 — 1 February 2010 © NXP B.V. 2010. All rights reserved ...
Page 4
... LPC1764FBD100 LQFP100 4.1 Ordering options Table 2. Ordering options Type number Flash SRAM in kB CPU AHB LPC1769FBD100 512 kB 32 LPC1768FBD100 512 kB 32 LPC1767FBD100 512 kB 32 LPC1766FBD100 256 kB 32 LPC1765FBD100 256 kB 32 LPC1764FBD100 128 kB 16 LPC1769_68_67_66_65_64_4 Product data sheet Description plastic low profile quad flat package; 100 leads; body 14 × 14 × 1.4 mm plastic low profile quad flat package ...
Page 5
... APB slave group 1 SSP0 UART2/3 (1) I2S I2C2 RI TIMER TIMER2/3 EXTERNAL INTERRUPTS SYSTEM CONTROL MOTOR CONTROL PWM (1) DAC QUADRATURE ENCODER (1) LPC1769/68/67/66/65 only (2) LPC1769/68/67/66/64 only (3) LPC1764 USB device only (4) LPC1769/68/66/65/64 only CLKOUT SCK0 SSEL0 MISO0 MOSI0 RXD2/3 TXD2/3 3 × I2SRX 3 × I2STX TX_MCLK RX_MCLK SCL2 SDA2 4 × ...
Page 6
... I2SRX_CLK — Receive Clock driven by the master and received by the slave. Corresponds to the signal SCK in the I (LPC1769/68/67/66/65 only). RD2 — CAN2 receiver input. (LPC1769/68/66/65/64 only). CAP2[0] — Capture input for Timer 2, channel 0. Rev. 04 — 1 February 2010 32-bit ARM Cortex-M3 microcontroller ...
Page 7
... I2SRX_WS — Receive Word Select driven by the master and received by the slave. Corresponds to the signal WS in the I (LPC1769/68/67/66/65 only). TD2 — CAN2 transmitter output. (LPC1769/68/66/65/64 only). CAP2[1] — Capture input for Timer 2, channel 1. P0[6] — General purpose digital input/output pin. I2SRX_SDA — Receive data driven by the transmitter and read by the receiver ...
Page 8
... P0[22] — General purpose digital input/output pin. RTS1 — Request to Send output for UART1. Can also be configured RS-485/EIA-485 output enable signal. TD1 — CAN1 transmitter output. (LPC1769/68/66/65/64 only). P0[23] — General purpose digital input/output pin. AD0[0] — A/D converter 0, input 0. I2SRX_CLK — Receive Clock driven by the master and received by the slave ...
Page 9
... Pins 11, 12, and 13 of this port are not available. P1[0] — General purpose digital input/output pin. ENET_TXD0 — Ethernet transmit data 0. (LPC1769/68/67/66/64 only). P1[1] — General purpose digital input/output pin. ENET_TXD1 — Ethernet transmit data 1. (LPC1769/68/67/66/64 only). ...
Page 10
... SSEL0 — Slave Select for SSP0. P1[22] — General purpose digital input/output pin. MCOB0 — Motor control PWM channel 0, output B. USB_PWRD — Power Status for USB port (host power switch, LPC1769/68/66/65 only). MAT1[0] — Match output for Timer 1, channel 0. P1[23] — General purpose digital input/output pin. ...
Page 11
... PCAP1[1] — Capture input for PWM1, channel 1. MAT0[1] — Match output for Timer 0, channel 1. P1[30] — General purpose digital input/output pin. V — Monitors the presence of USB bus power. (LPC1769/68/66/65/64 only). BUS Note: This signal must be HIGH for USB reset to occur. AD0[4] — A/D converter 0, input 4. ...
Page 12
... TXD2 — Transmitter output for UART2. P2[9] — General purpose digital input/output pin. USB_CONNECT — Signal used to switch an external 1.5 kΩ resistor under software control. Used with the SoftConnect USB feature. (LPC1769/68/66/65/64 only). RXD2 — Receiver input for UART2. P2[10] — General purpose digital input/output pin. ...
Page 13
... TXD3 — Transmitter output for UART3. P4[29] — General purpose digital input/output pin. 2 TX_MCLK — transmit master clock. (LPC1769/68/67/66/65 only). MAT2[1] — Match output for Timer 2, channel 1. RXD3 — Receiver input for UART3. TDO — Test Data out for JTAG interface. ...
Page 14
... When the system oscillator is not used, connect XTAL1 and XTAL2 as follows: XTAL1 can be left floating or can be grounded (grounding is preferred to reduce susceptibility to noise). XTAL2 should be left floating. LPC1769_68_67_66_65_64_4 Product data sheet LPC1769/68/67/66/65/64 Description Output from the RTC oscillator circuit. ground reference. ...
Page 15
... The LPC17xx have a Memory Protection Unit (MPU) which can be used to improve the reliability of an embedded system by protecting critical data within the user application. LPC1769_68_67_66_65_64_4 Product data sheet LPC1769/68/67/66/65/64 32-bit ARM Cortex-M3 microcontroller Figure 1). The I-code and D-code core buses are faster than the Rev. 04 — ...
Page 16
... Each peripheral of either type is allocated space. This allows simplifying the address decoding for each peripheral. LPC1769_68_67_66_65_64_4 Product data sheet Figure 3 shows the overall map of the entire address space from the user Rev. 04 — 1 February 2010 LPC1769/68/67/66/65/64 32-bit ARM Cortex-M3 microcontroller © NXP B.V. 2010. All rights reserved ...
Page 17
... AHB SRAM0 0x2007 C000 0.5 GB reserved 0x1FFF 2000 8 kB boot ROM 0x1FFF 0000 reserved 0x1000 8000 32 kB local SRAM (LPC1769/8/7/6/5) 0x1000 4000 16 kB local SRAM (LPC1764) 0x1000 0000 reserved 0x0008 0000 512 kB on-chip flash (LPC1769/8/7) 0x0004 0000 256 kB on-chip flash (LPC1766/65) ...
Page 18
... AHB master. The GPDMA controller allows data transfers between the USB (LPC1769/68/66/65/64 only) and Ethernet controllers (LPC1769/68/67/66/64 only) and the various on-chip SRAM areas. The supported APB peripherals are SSP0/1, all UARTs, the I can be used to trigger DMA transfers ...
Page 19
... Entire port value can be written in one instruction. • Support for Cortex-M3 bit banding. • Support for use with the GPDMA controller. LPC1769_68_67_66_65_64_4 Product data sheet LPC1769/68/67/66/65/64 32-bit ARM Cortex-M3 microcontroller Rev. 04 — 1 February 2010 © NXP B.V. 2010. All rights reserved ...
Page 20
... Pull-up/pull-down resistor configuration and open-drain configuration can be programmed through the pin connect block for each GPIO pin. 7.11 Ethernet (LPC1769/68/67/66/64 only) Remark: The Ethernet controller is not available for part LPC1765. The Ethernet block contains a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC designed to provide optimized performance through the use of DMA hardware acceleration ...
Page 21
... Attachment of external PHY chip through standard RMII interface. – PHY register access is available via the MIIM interface. 7.12 USB interface (LPC1769/68/66/65/64 only) The Universal Serial Bus (USB 4-wire bus that supports communication between a host and one or more (up to 127) peripherals. The host controller allocates the USB bandwidth to attached devices through a token-based protocol ...
Page 22
... Supports SoftConnect and GoodLink features. • While USB is in the Suspend mode, the LPC1769/68/66/65/64 can enter one of the reduced power modes and wake up on USB activity. • Supports DMA transfers with all on-chip SRAM blocks on all non-control endpoints. ...
Page 23
... Optional conversion on transition of input pin or Timer Match signal. • Individual result registers for each ADC channel to reduce interrupt overhead. • DMA support. 7.15 10-bit DAC (LPC1769/68/67/66/65 only) The DAC allows to generate a variable analog output. The maximum output value of the DAC is VREFP. 7.15.1 Features • ...
Page 24
... SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given LPC1769_68_67_66_65_64_4 Product data sheet LPC1769/68/67/66/65/64 32-bit ARM Cortex-M3 microcontroller Rev. 04 — 1 February 2010 © NXP B.V. 2010. All rights reserved. ...
Page 25
... C2 use standard I/O pins with bit rates 400 kbit/s (Fast I 2 C-bus can be used for test and diagnostic purposes. 2 C-bus controllers support multiple address recognition and a bus monitor mode. Rev. 04 — 1 February 2010 LPC1769/68/67/66/65/64 32-bit ARM Cortex-M3 microcontroller multi-master bus and can also 2 C-bus) ...
Page 26
... LPC1769_68_67_66_65_64_4 Product data sheet LPC1769/68/67/66/65/64 2 S-bus is not available on the LPC1764. 2 S-bus connection has one master, which is 2 S-bus interface on the LPC1769/68/67/66/65 Rev. 04 — 1 February 2010 32-bit ARM Cortex-M3 microcontroller 2 S-bus input and 2 S-bus input and I © NXP B.V. 2010. All rights reserved. ...
Page 27
... Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation. LPC1769_68_67_66_65_64_4 Product data sheet LPC1769/68/67/66/65/64 32-bit ARM Cortex-M3 microcontroller Rev. 04 — 1 February 2010 © NXP B.V. 2010. All rights reserved ...
Page 28
... Index compare register with interrupts. • Can combine index and position interrupts to produce an interrupt for whole and partial revolution displacement. LPC1769_68_67_66_65_64_4 Product data sheet LPC1769/68/67/66/65/64 32-bit ARM Cortex-M3 microcontroller Rev. 04 — 1 February 2010 © NXP B.V. 2010. All rights reserved ...
Page 29
... The Watchdog Clock (WDCLK) source can be selected from the Internal RC (IRC) oscillator, the RTC oscillator, or the APB peripheral clock. This gives a wide range of potential timing choices of Watchdog operation under different power reduction LPC1769_68_67_66_65_64_4 Product data sheet LPC1769/68/67/66/65/64 × 256 × cy(WDCLK) × 4. cy(WDCLK) Rev. 04 — ...
Page 30
... Following reset, the LPC17xx will operate from the Internal RC oscillator until switched by software. This allows systems to operate without any external crystal and the bootloader code to operate at a known frequency. LPC1769_68_67_66_65_64_4 Product data sheet LPC1769/68/67/66/65/64 32-bit ARM Cortex-M3 microcontroller Section 7.29.4) makes measuring the oscillator Rev. 04 — 1 February 2010 © ...
Page 31
... PLL enable select (CLKSRCSEL) WATCHDOG TIMER pclk WDT rtclk = 1Hz REAL-TIME CLOCK Section 7.29.2 for additional information. Rev. 04 — 1 February 2010 LPC1769/68/67/66/65/64 32-bit ARM Cortex-M3 microcontroller usbclk (48 MHz) USB CLOCK DIVIDER pllclk USB clock config USB PLL enable (USBCLKCFG) cclk CPU ...
Page 32
... This is important at power on, all types of Reset, and LPC1769_68_67_66_65_64_4 Product data sheet LPC1769/68/67/66/65/64 32-bit ARM Cortex-M3 microcontroller Rev. 04 — 1 February 2010 © NXP B.V. 2010. All rights reserved. ...
Page 33
... The PLL is automatically turned off and disconnected. The CCLK and USB clock dividers automatically get reset to zero. LPC1769_68_67_66_65_64_4 Product data sheet LPC1769/68/67/66/65/64 32-bit ARM Cortex-M3 microcontroller ramp (in the case of power on), the type of crystal and its DD(3V3) Rev. 04 — 1 February 2010 © ...
Page 34
... A Power Control for Peripherals feature allows individual peripherals to be turned off if they are not needed in the application, resulting in additional power savings. LPC1769_68_67_66_65_64_4 Product data sheet LPC1769/68/67/66/65/64 32-bit ARM Cortex-M3 microcontroller Rev. 04 — 1 February 2010 © NXP B.V. 2010. All rights reserved ...
Page 35
... V pins together. This approach requires only one 3.3 V power DD(REG)(3V3 used to operate the RTC whenever V Rev. 04 — 1 February 2010 LPC1769/68/67/66/65/64 32-bit ARM Cortex-M3 microcontroller ) pins, while the DD(3V3) ). Having the on-chip voltage regulator DD(REG)(3V3) is present ...
Page 36
... When the internal Reset is removed, the processor begins executing at address 0, which is initially the Reset vector mapped from the Boot Block. At that point, all of the processor and peripheral registers have been initialized to predetermined values. LPC1769_68_67_66_65_64_4 Product data sheet LPC1769/68/67/66/65/64 LPC17xx to I/O pads V DD(3V3) ...
Page 37
... The APB peripherals are split into two separate APB buses in order to distribute the bus bandwidth and thereby reducing stalls caused by contention between the CPU and the GPDMA controller. LPC1769_68_67_66_65_64_4 Product data sheet LPC1769/68/67/66/65/64 32-bit ARM Cortex-M3 microcontroller pins falls below 2.65 V. This reset prevents alteration of DD(REG)(3V3) Rev. 04 — 1 February 2010 pins ...
Page 38
... JTAG debug and parallel trace functions. The ARM Cortex-M3 is configured to support up to eight breakpoints and four watch points. LPC1769_68_67_66_65_64_4 Product data sheet LPC1769/68/67/66/65/64 32-bit ARM Cortex-M3 microcontroller Rev. 04 — 1 February 2010 © NXP B.V. 2010. All rights reserved ...
Page 39
... The peak current is limited to 25 times the corresponding maximum current. [5] Dependent on package type. [6] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor. LPC1769_68_67_66_65_64_4 Product data sheet LPC1769/68/67/66/65/64 32-bit ARM Cortex-M3 microcontroller [1] Conditions core and external rail for the RTC ...
Page 40
... I/O power dissipation ° ° +85 C unless otherwise specified; Conditions Rev. 04 — 1 February 2010 LPC1769/68/67/66/65/64 32-bit ARM Cortex-M3 microcontroller (°C), can be calculated using the following j and V . The I/O power dissipation Min ...
Page 41
... BAT I I/O supply current DD(IO) I ADC supply current DD(ADC) I ADC input current I(ADC) LPC1769_68_67_66_65_64_4 Product data sheet LPC1769/68/67/66/65/64 Conditions core and external rail [2] active mode; code while(1){} executed from flash; all peripherals disabled; ⁄ CCLK PCLK = 8 [3] CCLK = 12 MHz; PLL ...
Page 42
... DD(3V3 0 DD(3V3 < V < DD(3V3 OLS DD(3V3 Rev. 04 — 1 February 2010 LPC1769/68/67/66/65/64 32-bit ARM Cortex-M3 microcontroller [1] Min Typ - - - - - - [12][13 [14 2 0.4 - − [15 DD(3V3) 0.4 [15 −4 [15] - [15] 4 ...
Page 43
... Oscillator pins V input voltage on pin i(XTAL1) XTAL1 V output voltage on pin o(XTAL2) XTAL2 V input voltage on pin i(RTCX1) RTCX1 V output voltage on pin o(RTCX2) RTCX2 USB pins (LPC1769/68/66/65/64 only) I OFF-state output OZ current V bus supply voltage BUS V differential input DI sensitivity voltage V differential common CM mode voltage range V ...
Page 44
... 0.2 Conditions DD(REG)(3V3) DD(3V3) Typical LOW-level output current I Rev. 04 — 1 February 2010 LPC1769/68/67/66/65/64 32-bit ARM Cortex-M3 microcontroller 16 I (mA 3.3 V; standard port pins. versus HIGH-level output source current °C 25 °C −40 °C 0 3.3 V; standard port pins. ...
Page 45
... ° °C −40 ° − Conditions DD(REG)(3V3) DD(3V3) Typical pull-down current I pd Rev. 04 — 1 February 2010 LPC1769/68/67/66/65/64 32-bit ARM Cortex-M3 microcontroller 3.3 V; standard port pins 3.3 V; standard port pins. versus input voltage V I 002aaf108 5 V ...
Page 46
... Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages. [2] Fig 10. External clock timing (with an amplitude of at least V LPC1769_68_67_66_65_64_4 Product data sheet Conditions powered unpowered [1] over specified ranges. Conditions t t CHCL CLCX i(RMS) Rev. 04 — 1 February 2010 LPC1769/68/67/66/65/64 32-bit ARM Cortex-M3 microcontroller Min Typ [1] 10 000 - [2] Min Typ × ...
Page 47
... Variations between parts may cause the DD(3V3) amb IRC to fall outside the 4 MHz ± accuracy specification for voltages below 2.7 V. [1] over specified ranges. Conditions pin configured as output pin configured as output Rev. 04 — 1 February 2010 LPC1769/68/67/66/65/64 32-bit ARM Cortex-M3 microcontroller [2] Min Typ 3.96 4.00 - 32.768 VDD(3V ...
Page 48
... Parameters are valid over operating temperature range unless otherwise specified. 2 [2] CCLK = PCLK = 20 MHz; I C-bus interface configured in master mode (50 pF), external pull-up resistance = 218 Ω. [3] Bus capacitance C b Fig 12 11.6 I S-bus interface (LPC1769/68/67/66/65 only) Table 12. Dynamic characteristics: I − ° ° +85 C. amb ...
Page 49
... NXP Semiconductors I2STX_CLK I2STX_SDA I2STX_WS Fig 13. I I2SRX_CLK I2SRX_SDA I2SRX_WS Fig 14. I LPC1769_68_67_66_65_64_4 Product data sheet LPC1769/68/67/66/65/64 T cy(clk v(Q) t v(Q) 2 S-bus timing (output) T cy(clk S-bus timing (input) Rev. 04 — 1 February 2010 32-bit ARM Cortex-M3 microcontroller su(D) ...
Page 50
... The peripheral clock for SSP is PCLK = CCLK = 20 MHz. shifting edges SCK MOSI MISO Fig 15. MISO line set-up time in SSP Master mode LPC1769_68_67_66_65_64_4 Product data sheet LPC1769/68/67/66/65/64 Conditions measured in SPI Master mode; see Figure 15 t su(SPI_MISO) Rev. 04 — 1 February 2010 32-bit ARM Cortex-M3 microcontroller ...
Page 51
... NXP Semiconductors 11.8 USB interface (LPC1769/68/66/65/64 only) Table 14. Dynamic characteristics: USB pins (full-speed) Ω pF 1 Symbol Parameter t rise time r t fall time f t differential rise and fall time FRFM matching V output signal crossover voltage CRS t source SE0 interval of EOP ...
Page 52
... SPI output data hold time × n) ± 0 the SPI clock divider value (n ≥ 8); PCLK is derived from the = (T cy(PCLK) SCK (CPOL = 0) SCK (CPOL = 1) MOSI MISO DATA VALID SPI master timing (CPHA = 1) Rev. 04 — 1 February 2010 LPC1769/68/67/66/65/64 32-bit ARM Cortex-M3 microcontroller Min Typ Max [1] 79 0.485 × ...
Page 53
... NXP Semiconductors Fig 18. Fig 19. LPC1769_68_67_66_65_64_4 Product data sheet LPC1769/68/67/66/65/64 SCK (CPOL = 0) SCK (CPOL = 1) t SPIQV DATA VALID MOSI DATA VALID MISO SPI master timing (CPHA = 0) T SPICYC SCK (CPOL = 0) SCK (CPOL = 1) MOSI DATA VALID t SPIQV MISO DATA VALID SPI slave timing (CPHA = 1) Rev. 04 — ...
Page 54
... See ) is the peak difference between the center of the steps of the actual and the ideal transfer curve after Figure 21. Figure Figure 21. Rev. 04 — 1 February 2010 LPC1769/68/67/66/65/64 32-bit ARM Cortex-M3 microcontroller SPICYC SPICLKH SPICLKL ...
Page 55
... Fig 21. 12-bit ADC characteristics LPC1769_68_67_66_65_64_4 Product data sheet (2) (5) (4) (3) 1 LSB (ideal (LSB ) IA ideal ). D ). Rev. 04 — 1 February 2010 LPC1769/68/67/66/65/64 32-bit ARM Cortex-M3 microcontroller (1) 4090 4091 4092 4093 4094 4095 VREFP − VREFN 1 LSB = 4096 offset gain error error 4096 002aad948 © ...
Page 56
... NXP Semiconductors Fig 22. ADC interface to pins AD0[n] 13. DAC electrical characteristics (LPC1769/68/67/66/65 only) Table 17. DAC electrical characteristics − 2 3 DDA amb Symbol Parameter E differential linearity error D E integral non-linearity L(adj) E offset error O E gain error G C load capacitance L R load resistance ...
Page 57
... NXP Semiconductors 14. Application information 14.1 Suggested USB interface solutions LPC17xx Fig 23. LPC1769/68/66/65/64 USB interface on a self-powered device LPC17xx Fig 24. LPC1769/68/66/65/64 USB interface on a bus-powered device LPC1769_68_67_66_65_64_4 Product data sheet LPC1769/68/67/66/65/64 32-bit ARM Cortex-M3 microcontroller V DD(3V3) USB_UP_LED USB_CONNECT SoftConnect switch R1 1.5 kΩ V BUS Ω ...
Page 58
... NXP Semiconductors RSTOUT LPC17xx USB_SCL USB_SDA EINTn USB_D+ USB_D− USB_UP_LED Fig 25. LPC1769/68/66/65 USB OTG port configuration USB_UP_LED USB_D+ USB_D− LPC17xx USB_PWRD USB_OVRCR USB_PPWR Fig 26. LPC1769/68/66/65 USB host port configuration LPC1769_68_67_66_65_64_4 Product data sheet LPC1769/68/67/66/65/ RESET_N ADR/PSW OE_N/INT_N V DD ...
Page 59
... LPC17xx USB_D+ USB_D− V BUS Fig 27. LPC1769/68/66/65/64 USB device port configuration 14.2 XTAL1 input The input voltage to the on-chip oscillators is limited to 1 the oscillator is driven by a clock in slave mode recommended that the input be coupled through a capacitor with C = 100 pF. To limit the input voltage to the specified range, choose an additional ...
Page 60
... scale (1) ( 0.27 0.20 14.1 14.1 16.25 16.25 0.5 0.17 0.09 13.9 13.9 15.75 15.75 REFERENCES JEDEC JEITA MS-026 Rev. 04 — 1 February 2010 LPC1769/68/67/66/65/64 32-bit ARM Cortex-M3 microcontroller detail 0.75 1.15 1 0.2 0.08 0.08 0.45 0.85 EUROPEAN PROJECTION SOT407 θ (1) (1) θ ...
Page 61
... RMII SE0 SPI SSI SSP TCM TTL UART USB LPC1769_68_67_66_65_64_4 Product data sheet LPC1769/68/67/66/65/64 Abbreviations Description Analog-to-Digital Converter Advanced High-performance Bus Advanced Microcontroller Bus Architecture Advanced Peripheral Bus BrownOut Detection Controller Area Network Digital-to-Analog Converter Debug Communication Channel Direct Memory Access ...
Page 62
... Table note 14 in Table 6 updated. • In Table 6, move parameter V • Added part LPC1769. • Added output pin parameters t • Added SRAM sizes for CPU SRAM, AHB SRAM0, and AHB SRAM1 in • Added table note for XTAL1 and XTAL2 pins in • Changed minimum value of parameters V − ...
Page 63
... This document supersedes and replaces all information supplied prior to the publication hereof. LPC1769_68_67_66_65_64_4 Product data sheet LPC1769/68/67/66/65/64 [3] Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. ...
Page 64
... NXP Semiconductors’ product specifications. 20. Contact information For more information, please visit: For sales office addresses, please send an email to: LPC1769_68_67_66_65_64_4 Product data sheet LPC1769/68/67/66/65/64 19.3 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners C-bus — ...
Page 65
... Fast general purpose parallel I 7.10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.11 Ethernet (LPC1769/68/67/66/64 only 7.11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.12 USB interface (LPC1769/68/66/65/64 only 7.12.1 USB device controller . . . . . . . . . . . . . . . . . . . 21 7.12.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.12.2 USB host controller (LPC1769/68/66/65 only 7.12.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.12.3 USB OTG controller (LPC1769/68/66/65 only 7.12.3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.13 CAN controller and acceptance filters (LPC1769/68/66/65/64 only 7.13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.14 12-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.15 10-bit DAC (LPC1769/68/67/66/65 only ...
Page 66
... SSP interface . . . . . . . . . . . . . . . . . . . . . . . . . 50 11.8 USB interface (LPC1769/68/66/65/64 only 11.9 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 12 ADC electrical characteristics . . . . . . . . . . . . 54 13 DAC electrical characteristics (LPC1769/68/67/66/65 only Application information 14.1 Suggested USB interface solutions . . . . . . . . 57 14.2 XTAL1 input . . . . . . . . . . . . . . . . . . . . . . . . . . 59 14.3 XTAL and RTCX Printed Circuit Board (PCB) layout guidelines . . . . . . . . . . . . . . . . . 59 15 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 60 16 Abbreviations ...