LPC1769 NXP Semiconductors, LPC1769 Datasheet - Page 36
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LPC1769
Manufacturer Part Number
LPC1769
Description
32-bit Arm Cortex-m3 Microcontroller; Up To 512 Kb Flash And 64 Kb Sram With Ethernet, Usb 2.0 Host/device/otg, Can
Manufacturer
NXP Semiconductors
Datasheet
1.LPC1769.pdf
(66 pages)
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NXP Semiconductors
LPC1769_68_67_66_65_64_4
Product data sheet
7.30.1 Reset
7.30 System control
Reset has four sources on the LPC17xx: the RESET pin, the Watchdog reset, power-on
reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt
trigger input pin. Assertion of chip Reset by any source, once the operating voltage attains
a usable level, starts the Wake-up timer (see description in
to remain asserted until the external Reset is de-asserted, the oscillator is running, a fixed
number of clocks have passed, and the flash controller has completed its initialization.
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the Boot Block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
Fig 5.
Power distribution
V
DD(REG)(3V3)
V
VREFN
DD(3V3)
RTCX1
RTCX2
VREFP
VBAT
V
V
V
DDA
SSA
SS
Rev. 04 — 1 February 2010
LPC17xx
RTC POWER DOMAIN
ADC POWER DOMAIN
MAIN POWER DOMAIN
OSCILLATOR
SELECTOR
to I/O pads
POWER
32 kHz
3.3 V REGULATOR
LPC1769/68/67/66/65/64
32-bit ARM Cortex-M3 microcontroller
REGULATOR
ULTRA-LOW
POWER
BACKUP REGISTERS
DAC
ADC
REAL-TIME CLOCK
Section
to core
to memories,
peripherals,
oscillators,
PLLs
7.29.5), causing reset
002aad978
© NXP B.V. 2010. All rights reserved.
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