HY27SA161G1M Hynix Semiconductor, HY27SA161G1M Datasheet
HY27SA161G1M
Related parts for HY27SA161G1M
HY27SA161G1M Summary of contents
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Document Title 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory Revision History No. 0.0 1) Initial Draft 0.1 1) Add 1.8V Operation Product to Data sheet 1) Change AC Characteristics - tWP(25ns->40ns), tWC(50ns->60ns), 0.2 - tRP(30ns->40ns), tRC(50ns->60ns), - tREADID(35ns->45ns) 1) Add ...
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FEATURES SUMMARY HIGH DENSITY NAND FLASH MEMORIES - Cost effective solutions for mass storage applications NAND INTERFACE - x8 or x16 bus width. - Multiplexed Address/ Data - Pinout compatibility for all densities SUPPLY VOLTAGE - 3.3V device: VCC = ...
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DESCRIPTION The HYNIX HY27(U/S)A(08/16)1G1M series is a family of non-volatile Flash memories that use NAND cell technology. The devices operate 3.3V and 1.8V voltage supply. The size of a Page is either 528 Bytes (512 + 16 spare) or 264 ...
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Vcc CE RE NAND WE Flash ALE CLE WP Vss Figure 1: Logic Diagram Address Register/Counter ALE CLE Command WE Interface CE Logic WP RE Command Register Rev 0.5 / Oct. 2004 HY27UA(08/16)1G1M Series HY27SA(08/16)1G1M Series 1Gbit (128Mx8bit / 64Mx16bit) ...
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Vcc Vcc ...
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Figure 5. 63-FBGA Contactions, x8 Device (Top view through package ...
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MEMORY ARRAY ORGANIZATION The memory array is made up of NAND structures where 16 cells are connected in series. The memory array is organized in blocks where each block contains 32 pages. The array is split into two areas, the ...
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SIGNAL DESCRIPTIONS See Figure 1, Logic Diagram and Table 1, Signal Names, for a brief overview of the signals connected to this device. Inputs/Outputs (I/O -I Input/Outputs are used to input the selected address, ...
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Ready/Busy (RB) The Ready/Busy output, RB open-drain output that can be used to identify if the Program/ Erase/ Read (PER) Controller is currently active. When Ready/Busy is Low read, program or erase operation is in ...
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Data Output Data Output bus operations are used to read: the data in the memory array, the Status Register, the Electronic Signa- ture and the Serial Number. Data is output when Chip Enable is Low, Write Enable is High, Address ...
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Table 2. Bus Operation BUS Operation CE ALE Command Input V IL Address Input V IL Data Input V IL Data Output V IL Write Protect X Standby V IH Note : (1) Only for x16 devices. (2) WP must ...
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COMMAND SET All bus write operations to the device are interpreted by the Command Interface. The Commands are input on I/O O and are latched on the rising edge of Write Enable when the Command Latch Enable signal is high. ...
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Once the Read A and Read C commands have been issued the pointer remains in the respective areas until another pointer code is issued. However, the Read B command is effective for only one operation, once an operation has been ...
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Read Memory Array Each operation to read the memory area starts with a pointer operation as shown in the Pointer Operations section. Once the area (main or spare) has been selected using the Read A, Read B or Read C ...
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CLE CE WE ALE RE RB 00h/ Address Input I/O 01h/ 50h Command Code Note less than 10ns, t ELWL WLWH Read A Command, x8 Devices Area B Area A (2nd half (1st half Page) Page) ...
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Busy time) RB 00h/ I/O Address Inputs 01h/50h Command Code Figure 12. Sequential Row Read Operation Read A Command, x8 Devices Read A Command, x8 Devices Read A Command, x8 Devices Area A Area A Area A Area ...
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Page Program The Page Program operation is the standard operation to program data to the memory array. The main area of the memory array is programmed by page, however partial page programming is allowed where any number of bytes (1 ...
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Copy Back Program The Copy Back Program operation is used to copy the data stored in one page and reprogram it in another page. The Copy Back Program operation does not require external memory and so the operation is faster ...
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Once the erase operation has completed the Status Register can be checked for errors. RB Block Address I/O 60h Inputs Block Erase Setup Code Reset The Reset command is used to reset the Command Interface and Status Register. If the ...
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P/E/R Controller Status Register bit SR6 has two different functions depending on the current operation. During all other operations SR6 acts as a P/E/R Controller bit, which indicates whether the P/E/R Controller is active or inactive. When the P/E/R Controller ...
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Table 6: Status Register Bit Bit NAME SR7 Write Protection Program/Erase/Read SR6 Controller Program/ Erase/ Read SR5 Controller SR4, SR3, SR2 Reserved SR0 Generic Error Read Electronic Signature The device contains a Manufacturer Code and Device Code. To read these ...
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Automatic Page 0 Read Description. At powerup, once the supply voltage has reached the threshold level, V state and the internal NAND device functions (reading, writing, erasing) are enabled. The device then automatically switches to read mode where ...
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Note: (1 equal to 2.5V for 3V Power Supply devices. CCth Figure 19. Automatic Page 0 Read at power-up (Sequential Row Read Enable) Bad Block Management Devices with Bad Blocks have the same quality level and the same ...
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Block Address= Figure 20. Bad Block Management Flowchart Table 8: Valid Block Symbol Para Valid Block VB PROGRAM AND ERASE TIMES AND ENDURANCE CYCLES The Program and Erase times and the number of Program/ Erase cycles per ...
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Table 9: Program, Erase Time and Program Erase Endurance Cycles Parameters Page Program Time Block Erase Time Program/Erase Cycles (per block) Data Retention MAXIMUM RATING Stressing the device above the ratings listed in Table 10, Absolute Maximum Ratings, may cause ...
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Table 11: Operating and AC Measurement Conditions Parameter Supply Voltage ( Ambient Temperature ( Load Capacitance ( TTL GATE and C L Input Pulses Voltages Input and Output Timing Ref. Voltages Input Rise and ...
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Table 13: DC Characteristics, 3.3V Device and 1.8V Device Parameter Symbol I Sequential Read CC1 Operating I Current Program CC2 I Erase CC3 I Stand-by Current (TTL) CC4 I Stand-By Current (CMOS) CC5 I Input Leakage Current LI I Output ...
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Table 14: AC Characteristics for Command, Address, Data Input (3.3V Device and 1.8V Device) Alt. Symbol Symbol t Address Latch Low to Write Enable Low ALLWL t ALS t Address Latch Hith to Write Enable Low ALHWL t Command Latch ...
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Table 15: AC Characteristics for Operation (3.3V Device and 1.8V Device) Alt. Symbol Symbol t t ALLRL1 AR1 Address Latch Low to Read Enable Low t t ALLRL2 AR2 t t Ready/Busy High to Read Enable Low BHRL RR t ...
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Alt. Symbol Symbol t t Write Enable High to Ready/Busy Low WHBL Write Enable High to Read Enable Low WHRL WHR Write Enable Low WLWL WC Write Enable Low Note: (1). The time to ...
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Setup time) CLE tELWL (CE Setup time) tWLWL CE tWLWH WE tALHWL tWHWL (ALE Setup time) tWHALL (ALE Hold time) ALE tDVWH (Data Setup time) Address I/O cycle 1 Figure 22. Address Latch AC Waveforms CLE CE tALLWL ...
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Cycle time) CE (RE High Holdtime) RE tRLQV (RE Accesstime) Data Out I/O tBHRL RB Figure 24. Sequential Data Output after Read AC Waveforms Note:1. CLE = Low, ALE = Low High. CLE tCLHWL CE tELWL WE ...
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CLE CE WE ALE RE I/O 90h Read Electronic 1st Cycle Signature Command Address Figure 26. Read Electronic Signature AC Waveform Note: Refer to table(To see Page 21) for the values of the manufacture and device codes. CLE CE tWHWL ...
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CLE CE WE ALE RE Add. M 50h I/O cycle 1 RB Command Code Figure 28. Read C Operation, One Page AC Waveform Note: 1. A0-A7 is the address in the Spare Memory area, where A0-A3 are valid and A4-A7 ...
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CLE CE tWLWL (Write Cycle time) WE ALE RE I/O 80h RB Page Program Address Input Setup Code Rev 0.5 / Oct. 2004 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash tWLWL N Data Input Figure 29. Page Program AC Waveform HY27UA(08/16)1G1M ...
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CLE CE tWLWL (Write Cycle time) WE ALE RE I/O RB Block Erase Block Address Input Setup Command WE ALE CLE RE I/O FFh RB Rev 0.5 / Oct. 2004 HY27UA(08/16)1G1M Series HY27SA(08/16)1G1M Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash ...
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System Interface Using CE don’t care To simplify system interface, CE may be deasserted during data loading or sequential data-reading as shown below. So possible to connect NAND Flash to a microprocessor. The only function that was removed ...
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Ready/Busy Signal Electrical Characteristics Figures 32, 33 and 34 show the electrical characteristics for the Ready/Busy signal. The value required for the resistor R can be calculated using the following equation: P where I is the sum of the input ...
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Figure 34. Resistor Value Waveform Timings for Ready/Busy Signal * Application Note Reset command must be issued when the controller writes data to another 512Mb.(i.e. When A26 is ...
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Figure 35. 48-TSOP1 - 48-lead Plastic Thin Small Outline 20mm, Package Outline Table 16: 48-TSOP1 - 48-lead Plastic Thin Small Outline 20mm, Package Mechanical Data Symbol ...
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Figure 36. 48-WSOP1 - 48-lead Plastic Very Very Thin Small Outline 17mm, Package Outline Table 17: 48-WSOP1- 48-lead Plastic Thin Small Outline 17mm, Package Mechanical Data Symbol ...
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Figure 39. 63-FBGA - 8.5 x 15mm, 6x8 ball array 0.8mm pitch, Pakage Outline Note: Drawing is not to scale. Table 17: 48-WSOP1 - 48-lead Plastic Thin Small Outline 17mm, Package Mechanical Data Symbol ...
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MARKING INFORMATION Packag TSOP1 / WSOP1 / FBGA - hynix - KOR - HY27xAxx121mTxB HY: HYNIX 27: NAND Flash x: Power Supply A: Classification xx: Bit Organization 1G: Density 1: Mode M: Version x: Package Type x: Package Material x: ...