HM-6642 Intersil Corporation, HM-6642 Datasheet

HM-6642

Manufacturer Part Number

HM-6642

Description

512x8 Cmos Prom

Manufacturer

Intersil Corporation

Datasheet

1.HM-6642.pdf (9 pages)

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512 x 8 CMOS PROM

The HM-6642/883 is a 512 x 8 CMOS NiCr fusible link

Programmable Read Only Memory in the popular 24 pin,

byte wide pinout. Synchronous circuit design techniques

combine with CMOS processing to give this device high

speed performance with very low power dissipation.

On-chip address latches are provided, allowing easy

interfacing with recent generation microprocessors that use

multiplexed address/data bus structures, such as the 8085.

The output enable controls, both active low and active high,

further simplify microprocessor system interfacing by

allowing output data bus control independent of the chip

enable control. The data output latches allow the use of the

HM-6642/883 in high speed pipelined architecture systems,

and also in synchronous logic replacement functions.

Applications for the HM-6642/883 CMOS PROM include low

power hand held microprocessor based instrumentation and

communications systems, remote data acquisition and

processing systems, processor control store, and

synchronous logic replacement.

All bits are manufactured storing a logical “0” and can be

selectively programmed for a logical “1” at any bit location.

Ordering Information

Pinouts

SBDIP

SLIM

SBDIP

CLCC

PKG.

RANGE (°C)

-55 to +125 HM1-6642B/883 HM1-6642/883 D24.6

-55 to +125 HM6-6642B/883 HM6-6642/883 D24.3

-55 to +125

TEMP.

GND

M-6642/883 (SBDIP)

TOP VIEW

120ns

Data Sheet

HM4-6642/883 J28.A

200ns

DWG. #

PKG.

1-888-INTERSIL or 321-724-7143

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Features

• This Circuit is Processed in Accordance to MIL-STD-883

• Low Power Standby and Operating Power

• Fast Access Time. . . . . . . . . . . . . . . . . . . . . . . 120/200ns

• Wide Operating . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

• Temperature Range

• Industry Standard Pinout

• Single 5.0V Supply

• CMOS/TTL Compatible Inputs

• Field Programmable

• Synchronous Operation

• On-Chip Address Latches

• Separate Output Enable

Pin Description

NOTE: P should be hardwired to GND except during programming.

A0-A8

G1, G2, G3

P (Note)

and is Fully Conformant Under the Provisions of

Paragraph 1.2.1.

- ICCSB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100µA

- ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA at 1MHz

All other trademarks mentioned are the property of their respective owners.

March 2004

Intersil (and design) is a registered trademark of Intersil Americas Inc.

HM-6642/883 (CLCC)

No Connect

Address Inputs

Chip Enable

Data Output

Power (+5V)

Output Enable

Program Enable

TOP VIEW

HM-6642/883

DESCRIPTION

FN3013.2

Related parts for HM-6642

HM-6642 Summary of contents

Page 1

... Data Sheet 512 x 8 CMOS PROM The HM-6642/883 is a 512 x 8 CMOS NiCr fusible link Programmable Read Only Memory in the popular 24 pin, byte wide pinout. Synchronous circuit design techniques combine with CMOS processing to give this device high speed performance with very low power dissipation. ...

Page 2

... ADDRESS ROW A5 REGISTER DECODER LATCHED 3 ADDRESS A1 A REGISTER HM-6642/883 MATRIX GATED COLUMN DECODER D 8-BIT DATA LATCH ALL LINES POSITIVE LOGIC - ACTIVE HIGH THREE STATE BUFFERS: A HIGH OUTPUT ACTIVE ...

Page 3

... CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. TABLE 1. HM-6642/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested ...

Page 4

... REFERENCE NOTE: G has the same timing as G except signal is inverted. Test Load Circuit DUT (NOTE) NOTE: TEST HEAD CAPACITANCE, INCLUDES STRAY AND JIG CAPACITANCE 4 HM-6642/883 TABLE 3. APPLICABLE SUBGROUPS METHOD 100%/5004 100%/5004 100%/5004 100%/5004 Samples/5005 Samples/5005 TAVQV TELAX ...

Page 5

... F3 2.4K 16 2.4K 15 VCC/2 2.4K VCC/2 14 2.4K 13 HM-6642/883 CLCC 1.5K 1.5K 1.5K 1.5K 1.5K 1.5K 1.5K 1.5K R1 HM-6642/883 (0.600 INCH) SBDIP VCC ...

Page 6

... METALLIZATION: Type Å Å ± 15k Thickness: 11k Metallization Mask Layout HM-6642/883 GLASSIVATION: Type: SiO Thickness: 8k WORST CASE CURRENT DENSITY: 1 HM-6642/883 VCC GND Å Å ± A/ ...

Page 7

... -E- 0.007 -H- - HM-6642/883 J28.A 28 PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE SYMBOL 0.010 PLANE 2 E3 PLANE ...

Page 8

... Measure dimension S2 from the top of the ceramic body to the nearest metallization or lead the maximum number of terminal positions. 9. Braze fillets shall be concave. 10. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 11. Controlling dimension: INCH. 8 HM-6642/883 D24.3 c1 LEAD FINISH 24 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE BASE (c) ...

Page 9

... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 9 HM-6642/883 D24.6 c1 LEAD FINISH ...

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