HM-6504 Intersil Corporation, HM-6504 Datasheet
HM-6504
Related parts for HM-6504
HM-6504 Summary of contents
Page 1
... Gated inputs allow lower operating current and also elimi- nate the need for pull up or pull down resistors. The HM-6504/883 is a fully static RAM and may be maintained in any state for an indefinite period of time. Data retention supply voltage and supply current are guaran- teed over temperature ...
Page 2
... NOTES: 1. All lines active high-positive logic. 2. Three-state Buffers: A high output active. 3. Control and Data Latches: L low and Q latches on rising edge Address Latches: Latch on falling edge Gated Decoders: Gate on rising edge of G. HM-6504/883 A 6 GATED ROW MATRIX 64 DECODER ...
Page 3
... CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Operating Conditions Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range . . . . . . . . . . . . . . . . -55 TABLE 1. HM-6504/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested PARAMETER SYMBOL Output Low Voltage ...
Page 4
... TABLE 2. HM-6504/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested (NOTES 1, 2) PARAMETER SYMBOL CONDITIONS (1) Chip Enable TELQV VCC = 4.5 and Access Time 5.5V Address Access (2) TAVQV VCC = 4.5 and Time 5.5V, Note 3 Chip Enable (5) TELEH VCC = 4.5 and Pulse Negative 5.5V Width Chip Enable (6) TEHEL VCC = 4.5 and Pulse Positive 5 ...
Page 5
... TABLE 3. HM-6504/883 ELECTRICAL PERFORMANCE SPECIFICATIONS PARAMETER SYMBOL Input Capacitance CI Output CO Capacitance Chip Enable Output (3) TELQX Disable Time Chip Enable Output (4) TEHQZ Disable Time Write Enable Read (12) TWHEL Mode Setup Time High Level Output VOHL Voltage NOTE: 1. The parameters listed in Table 3 are controlled via design, or process parameters are characterized upon initial design and after major process and/or design changes ...
Page 6
... The address information is latched in the on-chip registers on the falling edge 0). Minimum address set up and hold time requirements must be met. After the required hold time, the addresses may change state without affecting device operation. During time ( the output becomes HM-6504/883 (8) TELEL (18) TELEH (5) ...
Page 7
... The logic value the time E falls determines the state of the output buffer for that cycle. Since W is low when E falls, the output buffer is latched into the high impedance state and will remain in that HM-6504/883 (8) (18) TELEL (5) TELEH ...
Page 8
... The late write cycle is a cross between the early write cycle and the read-modify-write cycle. Recall that in the early write, the output is guaranteed to remain high impedance, and in the read-modify-write, the output is guaranteed valid at access time. The late write is HM-6504/883 (8) TELAX (18) TELEL (5) TELEH ...
Page 9
... NOTES: All resistors 47k 5 100kHz 10 F12 = F11 VCC = 5.5V 0.5V. VIH = 4.5V 10%. VIL = -0.2V to +0.4V 0.01 F Min. HM-6504/883 + IOH 1.5V - EQUIVALENT CIRCUIT HM-6504/883 CERDIP VCC VCC F10 F11 F12 A4 A9 ...
Page 10
... No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com HM-6504/883 WORST CASE CURRENT DENSITY 1. A/cm LEAD TEMPERATURE (10s soldering): o 300 C HM-6504/883 A1 A0 VCC A6 W GND E D 6-143 A7 A8 ...