HM-65262 Intersil Corporation, HM-65262 Datasheet

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HM-65262

Manufacturer Part Number
HM-65262
Description
16k X 1 Asynchronous Cmos Static Ram
Manufacturer
Intersil Corporation
Datasheet
March 1997
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
Features
• Fast Access Time. . . . . . . . . . . . . . . . . . . . 70/85ns Max
• Low Standby Current. . . . . . . . . . . . . . . . . . . .50 A Max
• Low Operating Current . . . . . . . . . . . . . . . . . 50mA Max
• Data Retention at 2.0V . . . . . . . . . . . . . . . . . . .20 A Max
• TTL Compatible Inputs and Outputs
• JEDEC Approved Pinout
• No Clocks or Strobes Required
• Temperature Range . . . . . . . . . . . . . . . +55
• Equal Cycle and Access Time
• Single 5V Supply
• Gated Inputs-No Pull-Up or Pull-Down Resistors
Ordering Information
NOTE:
Pinouts
CERDIP
CLCC (SMD#)
1. Access Time/Data Retention Supply Current.
Required
GND
JAN #
SMD#
A0
A1
A2
A3
A4
A5
A6
W
Q
PACKAGE
HM-65262 (CERDIP)
10
1
2
3
4
5
6
7
8
9
TOP VIEW
-55
-55
-55
20
19
18
17
16
15
14
13
12
11
TEMP. RANGE
-40
o
o
o
V
A13
A12
A11
A10
A9
A8
A7
D
E
o
C to +125
C to +125
C to +125
CC
C to +85
|
Copyright
o
o
o
o
C
C
C
C
©
Intersil Corporation 1999
70ns/20 A (NOTE 1) 85ns/20 A (NOTE 1)
HM1-65262B-9
29109BRA
8413203RA
8413203YA
A2
A3
A4
A5
A6
Q
o
C to +125
3
4
5
6
7
8
HM-65262 (CLCC)
9 10 11 12
2
TOP VIEW
1
20
o
C
6-1
19
HM1-65262-9
29103BRA
8413201RA
8413201YA
Description
The HM-65262 is a CMOS 16384 x 1-bit Static Random
Access Memory manufactured using the Intersil Advanced
SAJI V process. The device utilizes asynchronous circuit
design for fast cycle times and ease of use. The HM-65262
is available in both JEDEC standard 20 pin, 0.300 inch wide
CERDIP and 20 pad CLCC packages, providing high board-
level packing density. Gated inputs lower standby current,
and also eliminate the need for pull-up or pull-down resis-
tors.
The HM-65262, a full CMOS RAM, utilizes an array of six
transistor (6T) memory cells for the most stable and lowest
possible standby supply current over the full military temper-
ature range. In addition to this, the high stability of the 6T
RAM cell provides excellent protection against soft errors
due to noise and alpha particles. This stability also improves
the radiation tolerance of the RAM over that of four transistor
(4T) devices.
18
17
16
15
14
13
A12
A11
A10
A9
A8
A7
HM-65262
V
A0 - A13
SS
85ns/400 A
V
W
(NOTE 1)
Q
D
E
/GND
CC
16K x 1 Asynchronous
-
-
-
-
Chip Enable/Power Down
Data Out
Data In
Ground
Power (+5)
Write Enable
CMOS Static RAM
Address Input
File Number
F20.3
F20.3
F20.3
J20.C
PKG. NO.
3002.2

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HM-65262 Summary of contents

Page 1

... C to +125 C The HM-65262, a full CMOS RAM, utilizes an array of six transistor (6T) memory cells for the most stable and lowest possible standby supply current over the full military temper- ature range. In addition to this, the high stability of the 6T RAM cell provides excellent protection against soft errors due to noise and alpha particles ...

Page 2

... Functional Diagram A12 A13 HM-65262 A 7 ROW ROW ADDRESS DECODER MEMORY ARRAY 128 (1 OF 128) BUFFER 128 X 128 A 7 128 COLUMN DECODER (1 OF 128) AND CIRCUITRY COLUMN ADDRESS BUFFERS 6 ...

Page 3

... CERDIP Package . . . . . . . . . . . . . . . . . . CC CLCC Package Maximum Storage Temperature Range . . . . . . . . . . . . . -65 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +175 Maximum Lead Temperature (Soldering 10s +300 Die Characteristics Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26256 Gates Operating Temperature Range HM-65262B-9, HM-65262-9, HM-65262C .- 10 - +85 C (HM-65262B-9, HM-65262-9, HM-65262C-9) A LIMITS MIN MAX ...

Page 4

... Input pulse levels 3.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate equivalent and C = 50pF (min) - for Tested at initial design and after major design changes 4.5 and 5.5V. CC HM-65262 10%, +85 C (HM-65262B-9, HM-65262-9, HM-65262C-9) A LIMITS HM-65262B-9 HM-65262-9 MIN MAX MIN MAX ...

Page 5

... TELQX xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx Q xxxxxxxxxxxxxxxxxxx NOTE this mode, E rises after W. The address must remain stable whenever both E and W are low. FIGURE 3. WRITE CYCLE 1: CONTROLLED BY W (LATE WRITE) HM-65262 (3) TELQV (5) TEHQX xxxxxxxxxx xxxxxxxxxx xxxxxxxxxx FIGURE 1. READ CYCLE 1: CONTROLLED BY E (1) TAVAX (2) TAVQV xxxxxxx ...

Page 6

... Chip Enable (E) must be held high during data retention; within +0.3V RAMs which have selects or output enables (e.g., S, G), one of the selects or output enables should be held 4.5V xxxxxxxxxxxx xxxxxxxxxxxx xxxxxxxxxxxx E HM-65262 (8) TAVAX (20) TAVEH (21) TELEH (22) TWLEH xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx (23) TDVEH xxxxxxxx (4) TELQX xxxxxxxx xxxxxxxx (15) TWLQZ the deselected state to keep the RAM outputs high impedance, minimizing power dissipation ...

Page 7

... No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 HM-65262 V = 2.0V CC -55 -35 - ...

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