HN29V1G91T-30 Renesas Electronics Corporation., HN29V1G91T-30 Datasheet - Page 6

• Manufacturer Part Number: HN29V1G91T-30
• Description: 128m X 8-bit Ag-and Flash Memory
• Manufacturer: Renesas Electronics Corporation.

HN29V1G91T-30
Pin Functions
Chip Enable: +-
+- is used for the selection of the device.
It goes to the standby mode when +- goes to ‘H’ level when the device is in the Output disable state.
When the device is in the Busy state during Program or Erase or Read operation, +- signal is ignored and
the device does not return to the standby mode even if +- goes to High.
Read Enable: 4-
The 4- signal controls serial data output. Data is available t
after the falling edge of 4-.
REA
The internal address counter is also incremented by one (Address = Address + 1) on this falling edge.
Write Enable: 9-
9- is the signal to latch each data in the device from the I/O port.
Data are latched in the device on the rising edge of 9-.
Command Latch Enable: CLE
The CLE input signal is used to control loading of the operation mode command into the internal register.
The command is latched into the internal register from the I/O port on the rising edge of 9- when CLE is
high.
Address Latch Enable: ALE
The ALE input signal is used to control loading of the input address information or input data into the
internal address/data register.
Address is latched on the rising edge of 9- with ALE high and Data is latched with ALE low.
I/O port: I/O1 to I/O8
The I/O1 to I/O8 pins are used as a port for transferring address, command and input/output data to and
from the device.
Write Protect: 92
The 92 signal is used to protect the device from accidental programming or erasing. The 92 low reset
internal program/erase operation. It is usually used for protecting the data with the 92 low during the
power-on/off sequence when input signals are invalid.
Ready Busy: R/*
The R/* output signal indicates the status of the device operation. When it is low, it indicates that the
Program, Erase or Read operation is in process and returns to Ready state (R/* = H) after completion of
the operation.
The output buffer for this signal is an open-drain and has to be pulled up to V
with appropriate register.
CC
Rev.4.00, Jun.20.2004, page 6 of 89