MBM29LV160TE70TN Meet Spansion Inc., MBM29LV160TE70TN Datasheet - Page 27

• Manufacturer Part Number: MBM29LV160TE70TN
• Description: Flash Memory Cmos 16m 2m ? 8/1m ? 16 Bit
• Manufacturer: Meet Spansion Inc.

Ready/Busy Pin
Hardware Reset Pin
• RY/BY
The MBM29LV160TE/BE provides a RY/BY open-drain output pin as a way to indicate to the host system that
the Embedded Algorithms are either in progress or has been completed. If the output is low, the device is busy
with either a program or erase operation. If the output is high, the device is ready to accept any read/write or
erase operation. When the RY/BY pin is low, the devices will not accept any additional program or erase com-
mands with the exception of the Erase Suspend command. If the MBM29LV160TE/BE is placed in an Erase
Suspend mode, the RY/BY output will be high, by means of connecting with a pull-up resister to V
During programming, the RY/BY pin is driven low after the rising edge of the fourth WE pulse. During an erase
operation, the RY/BY pin is driven low after the rising edge of the sixth WE pulse. The RY/BY pin will indicate a
busy condition during the RESET pulse. See “RY/BY Timing Diagram during Program/Erase Operation Timing
Diagram” and “RESET, RY/BY Timing Diagram” in “■TIMING DIAGRAM” for a detailed timing diagram. The
RY/BY pin is pulled high in standby mode.
Since this is an open-drain output, RY/BY pins can be tied together in parallel with a pull-up resistor to V
• RESET
The MBM29LV160TE/BE device may be reset by driving the RESET pin to V
requirement and has to be kept low (V
Any operation in the process of being executed will be terminated and the internal state machine will be reset
to the read mode “t
device requires an additional “t
in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware
reset occurs during a program or erase operation, the data at that particular location will be corrupted. Please
note that the RY/BY output signal should be ignored during the RESET pulse. Refer to “RESET, RY/BY Timing
Diagram” in “■TIMING DIAGRAM” for the timing diagram. Refer to Temporary Sector Unprotection for additional
functionality.
If hardware reset occurs during Embedded Erase Algorithm, there is a possibility that the erasing sector(s) will
need to be erased again before they can be programmed.
• Byte/Word Configuration
The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the MBM29LV160TE/BE device. When
this pin is driven high, the device operates in the word (16-bit) mode. The data is read and programmed at DQ
to DQ
becomes the lowest address bit and DQ
an 8-bit operation and hence commands are written at DQ
“Timing Diagram for Word Mode Configuration”, “Timing Diagram for Byte Mode Configuration” and “BYTE
Timing Diagram for Write Operations” in “■TIMING DIAGRAM” for the timing diagram.
• Data Protection
The MBM29LV160TE/BE is designed to offer protection against accidental erasure or programming caused by
spurious system level signals that may exist during power transitions. During power up the device automatically
resets the internal state machine to the Read mode. Also, with its control register architecture, alteration of the
memory contents only occurs after successful completion of specific multi-bus cycle command sequence.
The device also incorporates several features to prevent inadvertent write cycles resulting form V
and power-down transitions or system noise.
• Low V
To avoid initiation of a write cycle during V
than V
disabled. Under this condition, the device will reset to the read mode. Subsequent writes will be ignored until
0
. When this pin is driven low, the device operates in byte (8-bit) mode. Under this mode, DQ
LKO
CC
(Min). If V
Write Inhibit
READY
CC
MBM29LV160TE
< V
” after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the
LKO
, the command register is disabled and all internal program/erase circuits are
RH
” before it allows read access. When the RESET pin is low, the device will be
Retired Product DS05-20883-7E_July 31, 2007
IL
14
) for at least “t
to DQ
CC
power-up and power-down, a write cycle is locked out for V
8
bits are tri-stated. However, the command bus cycle is always
RP
” in order to properly reset the internal state machine.
70/90
7
to DQ
/MBM29LV160BE
0
and DQ
15
to DQ
IL
. The RESET pin has a pulse
8
bits are ignored. Refer to
CC
CC
.
power-up
15
/A
CC
70/90
CC
-1
less
.
pin
15
27