MCD212 Motorola, MCD212 Datasheet - Page 22

• Manufacturer Part Number: MCD212
• Description: Video Decoder and System Controller(with JTAG)
• Manufacturer: Motorola

3.5
The VDSC is connected to the system bus via 22 address lines and upper and lower data strobes. The
address decoding is validated by CS.
3.6
A data transfer is initiated by an upper and/or lower data strobe (U/LDS) from the system. A data
transfer is acknowledged by the VDSC via DTACK. A data transfer is terminated by U/LDS becoming
inactive followed by DTACK becoming inactive.
The VDSC generates the data acknowledge (DTACK) depending on the addressed area:
If U/LDS becomes inactive before DTACK is generated by the VDSC, DTACK will not be generated.
MOTOROLA
Access to the DRAM is acknowledged as soon as it is certain that data can be read or written by the
Access to the system ROM is acknowledged after a programmable number of clock or CLK cycles. The
system.
DTACK delay is controlled by Control Register CSR1W.
ADDRESS DECODING
DATA ACKNOWLEDGE GENERATION
NOTE:The system ROM decoding asserts the CSROM pin that is not
h000000 – h3FFFFF
h400000 – h4FFBFF
h4FFC00 – h4FFFDF
h4FFFE0 – h4FFFEF
h4FFFF0 – h4FFFFF
sensitive to the R/W signal. This allows the use of static RAM in
the ROM mapping area. The system I/O decoding asserts the
CSIO pin.
Table 3–2. DTACK Delay for ROM
NOTE: Access to the SYSTEM I/O device (CSIO
DD
0
1
1
1
1
Table 3–1. Address Map
pin) is not acknowledged by the VDSC
but by the addressed device.
DD1
0
0
1
1
x
MCD212
DD2
DRAM (4M byte)
System ROM (1M byte)
System I/O (1K byte)
Channel 2 internal registers
Channel 1 internal registers
0
1
0
1
x
CLK Cycles
11
9
3
5
7
10
12
4
6
8
3–3