MCD212 Motorola, MCD212 Datasheet - Page 27

• Manufacturer Part Number: MCD212
• Description: Video Decoder and System Controller(with JTAG)
• Manufacturer: Motorola

4–4
4.3
The DRAM timing is based on the CLK clock (see Figure 4–3).
In the CH#1/CH#2 slot a burst of four words are read in fast page mode. If a page break occurs, the
burst is incomplete. In the system slot a random read or write is possible.
The memory address bus (MA) is multiplexed in order to present the row address on RAS falling edge
and the column address on CAS1 or CAS2 falling edge. The correspondence between memory ad-
dress bus, MA0 – MA9 and system address A1 – A22 is indicated in Table 4–2. CAS1 and CAS2
function as bank select signals (see Table 4–3).
MD0 – MD15
MD0 – MD15
MA0 – MA9
WRITE
READ
CAS1
CAS2
UWR
LWR
RAS
CLK
Ax = A10 for TD = 0 (256K x 4, 256K x 16)
Ax = A18 for TD = 1 (1M x 4)
DRAM TIMING
RAS
CAS
MA0
A11
TD = 0
TD = 1
A1
ROW
SYSTEM
Table 4–2. Memory Address Distribution
MA1
A12
A2
Table 4–3. CAS1 and CAS2 Assertion
CAS1 asserted if validated and A18 = 0, A19 = 0, A20 = 0, A22 = 0
CAS2 asserted if validated and A18 = 1, A19 = 0, A20 = 0, A22 = 0
CAS1 asserted if validated and A20 = 0, A22 = 0
CAS2 asserted if validated and A20 = 1, A22 = 0
Ö Ö
Ö Ö
COL
MA2
Figure 4–3. DRAM Timing
A13
A3
MA3
A14
A4
MCD212
ROW
MA4
A15
A5
Ö Ö Ö
Ö Ö Ö
COL
MA5
A16
A6
CH#1 OR CH#2
Ö Ö Ö
Ö Ö Ö
MA6
A17
A7
COL
MA7
A18
A8
COL
Ö Ö
Ö Ö
MA8
A9
Ax
Ö Ö
Ö Ö
MA9
A19
A10
COL
MOTOROLA