MCD212 Motorola, MCD212 Datasheet - Page 23

• Manufacturer Part Number: MCD212
• Description: Video Decoder and System Controller(with JTAG)
• Manufacturer: Motorola

3–4
3.7
The BERR signal is asserted if enabled by writing a 1 in the BE (bus error) bit of the control register
CSR1W and if a data transfer is not acknowledged for at least one entire video line (approximately
64 s) after selection. The BE flag bit is then set in the CSR2R register. The BERR pin is released as
soon as the CPU releases UDS and LDS. The BE flag is reset when the CPU reads the CSR2R status
register.
3.8
The VDSC can generate interrupts to the CPU by asserting its INT pin. The following conditions can
generate an interrupt:
The IT1 bit and IT2 bit are reset after the CPU reads the CSR2R register. The INT pin is inactive when
both IT1 and IT2 are reset (see equation above).
The ICA1/DCA1 controller fetches an interrupt instruction. Then, the IT1 bit of the CSR2R register is
The ICA2/DCA2 controller fetches an interrupt instruction. Then, the IT2 bit of the CSR2R register is
set. If the DI1 bit in the CSR1W register is reset to 0, the IT1 bit of the CSR2R register can generate
an interrupt on the INT pin.
set. If the DI2 bit in the CSR2W register is reset to 0, the IT2 bit of the CSR2R register can generate
an interrupt on the INT pin.
BE FLAG BIT
BUS ERROR GENERATION
INTERRUPT GENERATION
DTACK
U/LDS
BERR
INT = not((not(DI1) and IT1) or (not(DI2) and IT2))
t 1 VIDEO LINE
Figure 3–4. Bus Error Timing
NO DTACK
MCD212
READ CSR2R
MOTOROLA