MCD212 Motorola, MCD212 Datasheet - Page 67

• Manufacturer Part Number: MCD212
• Description: Video Decoder and System Controller(with JTAG)
• Manufacturer: Motorola

9–4
CSR2R (read, 4FFFE1)
9.1.3
The Display Command Registers group control bits for the display and six MSBs of the Video start
address.
The eight MSBs are reset to 0 after the RESET sequence.
DCR1 (write, 4FFFF2)
IT1
IT2
BE
DE
CF
FD
SM
DE
15
Display Command Registers DCR1 and DCR2
CF
14
Table 9–8. Display Command Register DCR1 — Write, 4FFFF2
FD
13
Table 9–7. Status Register CSR2R — Read, 4FFFE1
(Interrupt1) This bit can be set to 1 by the ICA/DCA mechanism to generate
an interrupt to the CPU. At the same time, the INT pin goes low, if the DI1
bit is set to 1 in the CSR1 register. The IT1 bit and the INT pin will be reset
automatically when the CPU reads the status register.
(Interrupt2) This bit can be set to 1 by the ICA/DCA mechanism to generate
an interrupt to the CPU. At the same time, the INT pin goes low, if the DI2
bit is set to 1 in the CSR2 register. The IT2 bit and the INT pin will be reset
automatically when the CPU reads the status register.
(Bus Error) This bit is set to 1 when a bus error condition has been gener-
ated by the watchdog timer. This bit is automatically reset after a status read
operation.
(Display Enable) Enables display access to DRAM and enables synchro-
nization outputs when set to 1.
(Crystal Frequency) Must be programmed as a function of the crystal oscilla-
tor frequency as follows.
(Frame Duration) When reset to 0, a 50 Hz scan is generated. When set
to 1, a 60 Hz scan frequency is generated.
(Scan Mode) This bit is used to select the scan mode.
SM
12
CM1
11
—
7
Table 9–9. Crystal Frequency
10
0
—
6
CF
IC1
0
1
9
—
5
DC1
MCD212
Frequency in MHz
—
8
4
30, 30.2097
—
—
3
7
28
IT1
2
—
6
IT2
A21
1
5
BE
0
A20
4
A19
3
A18
2
A17
1
A16
0
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