STE100A ST Microelectronics, Inc., STE100A Datasheet - Page 33

• Manufacturer Part Number: STE100A
• Description: PCI 10/100 Ethernet Controller with Integrated PHY (3.3v)
• Manufacturer: ST Microelectronics, Inc.

STE10/100A
Table 6.
R/W: Read and write able. RO: Read able only.
CR2 (offset = 08h), CC - Class code and revision number
RO: Read only
31~24
23~16
19~ 9
15~ 8
7 ~ 4
3 ~ 0
Bit #
5~ 3
20
8
7
6
2
1
0
CIOSA
Configuration registers description (continued)
CMSA
Name
CMO
CSE
CPE
BCC
NC
SC
RN
SN
---
---
---
---
New capabilities. Indicates whether the STE10/100A
provides a list of extended capabilities, such as PCI
power management.
1: the STE10/100A provides the PCI management
function.
0: the STE10/100A doesn’t provide new capabilities.
Reserved
Command system error response.
1: enable system error response. The STE10/100A
will assert SERR# when it finds a parity error during
the address phase.
Reserved
Command parity error response.
0: disable parity error response. STE10/100A will
ignore any detected parity error and keep on
operating. Default value is 0.
1: enable parity error response. STE10/100A will
assert system error (bit 13 of CSR5) when a parity
error is detected.
Reserved
Command master operation ability.
0: disable the STE10/100A bus master ability.
1: enable the PCI bus master ability. Default value is
1 for normal operation.
Command memory space access.
0: disable the memory space access ability.
1: enable the memory space access ability.
Command I/O space access.
0: enable the I/O space access ability.
1: disable the I/O space access ability.
Base class code. It means STE10/100A is a network
controller.
Subclass code. It means STE10/100A is a fast
ethernet controller.
Reserved
Revision number, identifies the revision number of
STE10/100A
Step number, identifies the STE10/100A steps
within the current revision
Description
Registers and descriptors description
Same as
bit 19 of
Default
CSR18
02h
00h
Ah
1h
1
0
1
1
1
RW type
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
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