STE100A ST Microelectronics, Inc., STE100A Datasheet - Page 63

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STE100A

Manufacturer Part Number
STE100A
Description
PCI 10/100 Ethernet Controller with Integrated PHY (3.3v)
Manufacturer
ST Microelectronics, Inc.
Datasheet
STE10/100A
Table 10.
XR7(offset = d0h) - XMC, XCVR mode control
XR8(offset = d4h) - XCIIS, XCVR configuration information and interrupt status
15~12
15~10
10~0
Bit #
11
9
8
7
6
5
4
3
2
1
DUPLEX
SPEED
PAUSE
Transceiver registers description (continued)
ANAR
ANPR
Name
ANC
RFD
PDF
----
LD
LS
---
---
Reserved
Long distance mode of 10BASE-T.
0: normal squelch level.
1: reduced 10Base-T squelch level for extended
cable length.
Reserved
Reserved
Speed configuration setting.
0: the speed is 10Mb/s.
1: the speed is 100Mb/s.
Duplex configuration setting.
0: the duplex mode is half.
1: the duplex mode is full.
PAUSE function configuration setting for flow
control.
0: PAUSE function is disabled.
1: PAUSE function is enabled
Auto-negotiation completed interrupt.
0: Auto-negotiation has not completed yet.
1: Auto-negotiation has completed.
Remote fault detected interrupt.
0: there is no remote fault detected.
1: remote fault is detected.
Link fail interrupt.
0: link test status is up.
1: link is down.
Auto-negotiation acknowledge received
interrupt.
0: there is no link code word received.
1: link code word is receive from link partner.
Parallel detection fault interrupt.
0: there is no parallel detection fault.
1: parallel detection is fault.
Auto-negotiation page received interrupt.
0: there is no auto-negotiation page received.
1: auto-negotiation page is received.
Description
Registers and descriptors description
Default
0
0
0
0
1
0
0
0
0
0
0
0
0
RW type
RO/LH*
RO/LH*
RO/LH*
RO/LH*
RO/LH*
RO/LH*
R/W
RO
RO
RO
RO
RO
RO
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