STE100A ST Microelectronics, Inc., STE100A Datasheet - Page 54

• Manufacturer Part Number: STE100A
• Description: PCI 10/100 Ethernet Controller with Integrated PHY (3.3v)
• Manufacturer: ST Microelectronics, Inc.

Registers and descriptors description
54/82
Table 8.
17~7
Bit #
3~2
19
18
6
5
4
1
0
PAUSE
Control/status register description (continued)
Name
ATUR
WOL
RWP
SINT
RTE
DRT
PM
---
Power management. Enables the STE10/100A
power management abilities. When this bit is set
into “0” the STE10/100A will set the Cap_Ptr
register to zero, indicating no PCI compliant
power management capabilities. The value of
this bit will be mapped to NC (CR1 bit 20). In PCI
power management mode, the wake up frames
include “Magic Packet”, “Unicast”, and
“Muliticast”.
Wake on LAN mode enable. When this bit is set
to ‘1’, then the STE10/100A enters wake on LAN
mode and enters the sleep state.
Once the STE10/100A enters the sleep state, it
remains there until: the wake up event occurs,
the WOL bit is cleared, or a reset (software or
hardware) happens.
In wake on LAN mode the wake-up frame is
“Magic Packet” only.
Reserved
Reset wake-up pattern data register pointer
Disable or enable the PAUSE function for flow
control. The default value of PAUSE is
determined by the result of auto-negotiation. The
driver software can overwrite this bit to enable or
disable it after the auto-negotiation has
completed.
0: PAUSE function is disabled.
1: PAUSE function is enabled
Receive threshold enable.
1: the receive FIFO threshold is enabled.
0: disable the receive FIFO threshold selection in
DRT (bits 3~2), and the receive threshold is set
to the default 64 bytes.
Drain receive threshold
00: 32 bytes (8 DW)
01: 64 bytes (16 DW)
10: store-and -forward
11: reserved
Software interrupt.
1: enable automatically transmit-underrun
recovery.
Description
from EEPROM
from EEPROM
Depends on
the result of
negotiation
Default
auto-
01
X
X
0
0
0
0
STE10/100A
RW type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO