STE100A ST Microelectronics, Inc., STE100A Datasheet - Page 52

• Manufacturer Part Number: STE100A
• Description: PCI 10/100 Ethernet Controller with Integrated PHY (3.3v)
• Manufacturer: ST Microelectronics, Inc.

Registers and descriptors description
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Table 8.
LH* = High Latching and cleared by writing 1
CSR17 (offset = 84h), ACSR7- Assistant CSR7 (Interrupt enable register 2)
22~ 20
19~17
25~17
14~0
Bit #
16
15
31
30
29
28
27
26
ANISS
Control/status register description (continued)
AAISS
PFRIE
Name
REIE
TDIE
TEIE
XIE
RS
TS
---
---
Transmit state. Reports the current transmission
state only, no interrupt will be generated.
000: stop
001: read descriptor
010: transmitting
011: FIFO fill, read the data from memory and
put into FIFO
100: reserved
101: reserved
110: suspended, unavailable transmit descriptor
or FIFO overflow
111: write descriptor
Receive state. Reports current receive state
only, no interrupt will be generated.
000: stop
001: read descriptor
010: check this packet and pre-fetch next
descriptor
011: wait for receiving data
100: suspended
101: write descriptor
110: flush the current FIFO
111: FIFO drain, move data from receiving FIFO
into memory
Added normal interrupt status summary.
1: whenever any of the added normal interrupts
occur.
Added abnormal interrupt status summary.
1: whenever any of the added abnormal
interrupts occur.
These bits are the same as the status register of
CSR5, and are accessible through either CSR5
or CSR16.
Transmit early interrupt enable
Receive early interrupt enable
Transceiver (XCVR) interrupt enable
Transmit deferred interrupt enable
Reserved
PAUSE frame received interrupt enable
Reserved
Description
Default
000
000
0
1
0
0
0
0
0
STE10/100A
RW type
RO/LH*
RO/LH*
R/W
R/W
R/W
R/W
R/W
RO
RO