S1D13505 Epson Electronics America, Inc., S1D13505 Datasheet
S1D13505
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S1D13505 Summary of contents
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... S1D13505 Embedded RAMDAC LCD/CRT Controller S1D13505 TECHNICAL MANUAL Document Number: X23A-Q-001-12 Copyright © 1998, 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products ...
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... Page 2 S1D13505 X23A-Q-001-12 THIS PAGE LEFT BLANK Epson Research and Development Vancouver Design Center TECHNICAL MANUAL Issue Date: 01/04/18 ...
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... Fax: 089-14005-110 Page 3 Taiwan Epson Taiwan Technology & Trading Ltd. 10F, No. 287 Nanking East Road Sec. 3, Taipei, Taiwan Tel: 02-2717-7360 Fax: 02-2712-9164 Singapore Epson Singapore Pte., Ltd. No. 1 Temasek Avenue #36-00 Millenia Tower Singapore, 039192 Tel: 337-7911 Fax: 334-2716 S1D13505 X23A-Q-001-12 ...
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... Page 4 S1D13505 X23A-Q-001-12 THIS PAGE LEFT BLANK Epson Research and Development Vancouver Design Center TECHNICAL MANUAL Issue Date: 01/04/18 ...
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... Simultaneous, Virtual and Split Screen Display are just some of the display modes supported, while the Hardware Cursor, Ink Layer, and the Memory Enhancement Registers offer substantial performance benefits. These features, combined with the S1D13505’s Operating System independence, make it an ideal display solution for a wide variety of applications. ...
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... S1D13505 SYSTEM BLOCK DIAGRAM Data and CPU Control Signals CONTACT YOUR SALES REPRESENTATIVE FOR THESE COMPREHENSIVE DESIGN TOOLS • S1D13505 Technical • Linux Console Driver Manual • S5U13505 Evaluation Boards • Windows CE Display Driver • CPU Independent Software • VXWorks Tornado ...
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... S1D13505 Embedded RAMDAC LCD/CRT Controller Hardware Functional Specification Document Number: X23A-A-001-14 Copyright © 1998, 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products ...
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... Page 2 S1D13505 X23A-A-001-14 THIS PAGE LEFT BLANK Epson Research and Development Vancouver Design Center Hardware Functional Specification Issue Date: 01/02/02 ...
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... DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2.11 Power Save . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2.12 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1 Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.2 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2.1 Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2.2 Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.2.3 LCD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.2.4 CRT Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.2.5 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.3 Summary of Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.4 Multiple Function Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.5 CRT Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6 D.C. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Hardware Functional Specification Issue Date: 01/02/02 Table of Contents Page 3 S1D13505 X23A-A-001-14 ...
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... TFT/D-TFD Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 7.5.11 CRT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 8.1 Register Mapping 8.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 8.2.1 Revision Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 8.2.2 Memory Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 8.2.3 Panel/Monitor Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 8.2.4 Display Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 S1D13505 X23A-A-001- Epson Research and Development Vancouver Design Center Hardware Functional Specification Issue Date: 01/02/02 ...
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... Image Manipulation in SwivelView . . . . . . . . . . . . . . . . . . . . . . . . . .136 13.3 Physical Memory Requirement 13.4 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138 14 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139 14.1 Maximum MCLK: PCLK Ratios . . . . . . . . . . . . . . . . . . . . . . . . . . .139 14.2 Frame Rate Calculation 14.3 Bandwidth Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143 15 Power Save Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 16 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 Hardware Functional Specification Issue Date: 01/02/ .123 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 . . . . . . . . . . . . . . . . . . . . . . . . . . .137 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 Page 5 S1D13505 X23A-A-001-14 ...
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... Page 6 S1D13505 X23A-A-001-14 THIS PAGE LEFT BLANK Epson Research and Development Vancouver Design Center Hardware Functional Specification Issue Date: 01/02/02 ...
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... Table 7-23: 4-Bit Single Monochrome Passive LCD Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . 77 Table 7-24: 8-Bit Single Monochrome Passive LCD Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . 79 Table 7-25: 4-Bit Single Color Passive LCD Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 7-26: 8-Bit Single Color Passive LCD Panel A.C. Timing (Format Hardware Functional Specification Issue Date: 01/02/02 List of Tables Page 7 S1D13505 X23A-A-001-14 ...
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... Table 7-29: 8-Bit Dual Monochrome Passive LCD Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . .89 Table 7-30: 8-Bit Dual Color Passive LCD Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . .91 Table 7-31: 16-Bit Dual Color Passive LCD Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . .93 Table 7-32: TFT/D-TFD A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 Table 8-1: S1D13505 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 Table 8-2: DRAM Refresh Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Table 8-3: Panel Data Width Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Table 8-4: FPLINE Polarity Selection ...
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... Single Monochrome Passive LCD Panel Timing . . . . . . . . . . . . . . . . . . . . . . 78 Figure 7-27: 8-Bit Single Monochrome Passive LCD Panel A.C. Timing . . . . . . . . . . . . . . . . . . . 79 Figure 7-28: 4-Bit Single Color Passive LCD Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Figure 7-29: 4-Bit Single Color Passive LCD Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . 81 Hardware Functional Specification Issue Date: 01/02/02 List of Figures Page 9 S1D13505 X23A-A-001-14 ...
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... Ink/Cursor Data Format 133 Figure 12-2: Cursor Positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Figure 13-1: Relationship Between The Screen Image and the Image Residing in the Display Buffer . . . . 135 Figure 16-1: Mechanical Drawing QFP15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 S1D13505 X23A-A-001-14 Epson Research and Development Vancouver Design Center Hardware Functional Specification Issue Date: 01/02/02 ...
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... Overview Description The S1D13505 is a color/monochrome LCD/CRT graphics controller interfacing to a wide range of CPUs and display devices. The S1D13505 architecture is designed to meet the low cost, low power requirements of the embedded markets, such as Mobile Communications, Hand-Held PCs, and Office Automation. The S1D13505 supports multiple CPUs, all LCD panel types, CRT, and additionally provides a number of differentiating features. Products requiring a “ ...
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... Registers are memory-mapped – the M/R# pin selects between the display buffer and register address space. • The complete 2M byte display buffer address space is addressable as a single linear address space through the 21-bit address bus. S1D13505 X23A-A-001-14 Epson Research and Development Vancouver Design Center ...
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... Single clock input for both the pixel and memory clocks. • Memory clock can be input clock or (input clock/2), providing flexibility to use CPU bus clock as input. • Pixel clock can be the memory clock, (memory clock/2), (memory clock/3) or (memory clock/4). Hardware Functional Specification Issue Date: 01/02/02 Page 13 S1D13505 X23A-A-001-14 ...
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... Output that can be used to control the LCD backlight. Power-on polarity is selected configuration pin. • Operating voltages from 2.7 volts to 5.5 volts are supported • 128-pin QFP15 surface mount package S1D13505 X23A-A-001-14 Epson Research and Development Vancouver Design Center Hardware Functional Specification ...
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... LCD FPFRAME FPFRAME Display FPLINE FPLINE DRDY MOD LCDPWR RED,GREEN,BLUE CRT HRTC Display VRTC IREF IREF FPDAT[15:8] UD[7:0] FPDAT[7:0] LD[7:0] 4/8/16-bit FPSHIFT FPSHIFT LCD Display FPFRAME FPFRAME FPLINE FPLINE DRDY MOD LCDPWR RED,GREEN,BLUE CRT HRTC Display VRTC IREF IREF X23A-A-001-14 Page 15 S1D13505 ...
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... CS# AB[20:1] DB[15:0] S1D13505F00A AB0# WE1# BS# RED,GREEN,BLUE RD/WR# WAIT# BUSCLK RESET# 256Kx16 FPM/EDO-DRAM . Power Oscillator Management M/R# FPDAT[15:8] CS# AB[20:0] DB[15:0] WE1# BS# S1D13505F00A RD/WR# RD# RED,GREEN,BLUE WE0# WAIT# BUSCLK RESET# 256Kx16 FPM/EDO-DRAM Epson Research and Development Vancouver Design Center UD[7:0] FPDAT[7:0] LD[7:0] 4/8/16-bit FPSHIFT FPSHIFT LCD Display FPFRAME FPFRAME FPLINE FPLINE DRDY MOD ...
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... LCD Display FPFRAME FPFRAME FPLINE FPLINE DRDY MOD LCDPWR RED,GREEN,BLUE CRT HRTC Display VRTC IREF IREF FPDAT[15:8] UD[7:0] FPDAT[7:0] LD[7:0] 4/8/16-bit FPSHIFT FPSHIFT LCD FPFRAME FPFRAME Display FPLINE FPLINE DRDY MOD LCDPWR RED,GREEN,BLUE CRT HRTC Display VRTC IREF IREF X23A-A-001-14 Page 17 S1D13505 ...
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... AB17 WE1# RD/WR# RED,GREEN,BLUE RD# WE0# WAIT# BUSCLK RESET# 1Mx16 FPM/EDO-DRAM . Power Oscillator Management M/R# CS# FPDAT[15:8] BS# AB[16:13] AB[12:0] DB[15:8] DB[7:0] AB20 AB19 S1D13505F00A AB18 AB17 WE1# RD/WR# RED,GREEN,BLUE RD# WE0# WAIT# BUSCLK RESET# 1Mx16 FPM/EDO-DRAM Epson Research and Development Vancouver Design Center UD[7:0] FPDAT[7:0] LD[7:0] 4/8/16-bit FPSHIFT FPSHIFT LCD Display FPFRAME FPFRAME ...
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... LCD Display FPFRAME FPFRAME FPLINE FPLINE DRDY MOD LCDPWR RED,GREEN,BLUE CRT HRTC Display VRTC IREF IREF FPDAT[15:8] UD[7:0] FPDAT[7:0] LD[7:0] 4/8/16-bit FPSHIFT FPSHIFT LCD FPFRAME FPFRAME Display FPLINE FPLINE DRDY MOD LCDPWR RED,GREEN,BLUE CRT HRTC Display VRTC IREF IREF X23A-A-001-14 Page 19 S1D13505 ...
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... The Host Interface (I/F) block provides the means for the CPU/MPU to communicate with the display buffer and internal registers via one of the supported bus interfaces. 4.2.3 CPU R/W The CPU R/W block synchronizes the CPU requests for display buffer access. If SwivelView is enabled, the data is rotated in this block. S1D13505 X23A-A-001-14 16-bit FPM/EDO-DRAM Memory Controller ...
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... The DAC is the Digital to Analog converter for analog CRT support. 4.2.11 Power Save The Power Save block contains the power save mode circuitry. 4.2.12 Clocks The Clocks module is the source of all clocks in the chip. Hardware Functional Specification Issue Date: 01/02/02 Page 21 S1D13505 X23A-A-001-14 ...
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... QFP15 surface mount package S1D13505 X23A-A-001- S1D13505 Figure 5-1: Pinout Diagram Epson Research and Development Vancouver Design Center ...
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... For PowerPC Bus, these pins input the system address bits 19 through 30 (A[19:30]). • For all other busses, these pins input the system address bits 12 C Hi-Z through 1 (A[12:1]). See “Host Bus Interface Pin Mapping” for summary. See the respective AC Timing diagram for detailed functionality. Page 23 at 5V/3.3V respectively) at 5V/3.3V) Description S1D13505 X23A-A-001-14 ...
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... I 113 AB19 I 112 AB20 I 111 S1D13505 X23A-A-001-14 Table 5-1: Host Interface Pin Descriptions (Continued) RESET# Cell State • For Philips PR31500/31700 Bus, these pins are connected to V • For Toshiba TX3912 Bus, these pins are connected to V • For PowerPC Bus, these pins input the system address bits 15 through 18 (A[15:18]) ...
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... For Toshiba TX3912 Bus, this pin is connected to V • For all other busses, this input pin is used to select between the C display buffer and register address spaces of the S1D13505. M/R# is Hi-Z set high to access the display buffer and low to access the registers. See Register Mapping. ...
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... This is a multi-purpose pin: • For SH-3/SH-4 Bus, this pin inputs the read write signal (RD/WR#). The S1D13505 needs this signal for early decode of the bus cycle. • For MC68K Bus 1, this pin inputs the read write signal (R/W#). • For MC68K Bus 2, this pin inputs the read write signal (R/W#). ...
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... For PowerPC Bus, this pin inputs the Transfer Size 1 signal (TSIZ1). • For PC Card (PCMCIA) Bus, this pin inputs the write enable signal (- WE). See “Host Bus Interface Pin Mapping” for summary. See the respective AC Timing diagram for detailed functionality. Page 27 Description . DD DD S1D13505 X23A-A-001-14 ...
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... Type Pin # WAIT RESET S1D13505 X23A-A-001-14 Table 5-1: Host Interface Pin Descriptions (Continued) RESET# Cell State The active polarity of the WAIT# output is configurable; the state of MD5 on the rising edge of RESET# defines the active polarity of WAIT# - see “Summary of Configuration Options”. ...
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... RESET# are used to configure the chip - see Summary of C/TS Hi-Z Configuration Options. Internal pull-down resistors (typical values of 1D 100K at 5V/3.3V respectively) pull the reset states to 0. External pull-up resistors can be used to pull the reset states to 1. See Memory Interface Timing for detailed functionality. Page 29 Description S1D13505 X23A-A-001-14 ...
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... MA9 IO 56 MA10 IO 59 MA11 IO 57 S1D13505 X23A-A-001-14 Table 5-2: Memory Interface Pin Descriptions (Continued) RESET# Cell State Multiplexed memory address - see Memory Interface Timing for CO1 0utput functionality. This is a multi-purpose pin: • For 2M byte DRAM, this is memory address bit 9 (MA9). ...
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... Vertical retrace signal for CRT A Analog output for CRT color Red A Analog output for CRT color Green A Analog output for CRT color Blue Current reference for DAC - see Analog Pins. This pin must be left A unconnected if the DAC is not needed. Page 31 Description Description S1D13505 X23A-A-001-14 ...
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... This pin can be used as a power-down input (SUSPEND output possibly used for controlling the LCD backlight power: • When MD9 = 0 at rising edge of RESET#, this pin is an Hi-Z if MD[9]=0 active-low Schmitt input used to put the S1D13505 into High if Hardware Suspend mode - see Section 15, “Power Save CS/TS1 MD[10:9]=01 Modes” ...
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... RESET# is used to configure: 1 16-bit host bus interface Big Endian WAIT# is active low (0 = insert wait state) SUSPEND# pin configured as SUSPEND# input Active high LCDPWR polarity or active low GPO polarity Primary Host Bus Interface Selected BUSCLK input not divided Page 33 (1/0) 0 S1D13505 X23A-A-001-14 ...
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... WE0# WE0# WE0 WAIT# WAIT# RDY DTACK# DSACK1# RESET# RESET# RESET# RESET# Note 1 The bus signal A0 is not used by the S1D13505 internally. S1D13505 X23A-A-001-14 Table 5-6: CPU Interface Pin Mapping Philips MC68K Generic MIPS/ISA PR31500 Bus 2 /PR31700 A20 A20 LatchA20 ...
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... Table 5-7: Memory Interface Pin Mapping FPM/EDO-DRAM Asym 256Kx16 2-CAS# 2-WE# 2-CAS# D[15:0] A[8:0] A9 GPIO1 GPIO2 UCAS# UWE# UCAS# LCAS# CAS# LCAS# WE# LWE# WE# RAS not used Sym 1Mx16 Asym 1Mx16 2-WE# 2-CAS# 2-WE# A9 A10 A11 UWE# UCAS# UWE# CAS# LCAS# CAS# LWE# WE# LWE# S1D13505 X23A-A-001-14 Page 35 ...
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... FPDAT11 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 FPDAT12] driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 FPDAT13 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 FPDAT14 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 FPDAT15 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 S1D13505 X23A-A-001-14 Table 5-8: LCD Interface Pin Mapping Color Passive Panel Single ...
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... Hardware Functional Specification Issue Date: 01/02/02 DAC 1.5k 1% 4.6 mA 2N2222 140 DAC V DAC 290 1% DAC CRT 150 1% DAC V SS Figure 5-3: External Circuitry for CRT Interface DAC V = 2. LM334 1N457 DAC Page 37 S1D13505 X23A-A-001-14 ...
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... V Output Voltage OUT T Storage Temperature STG T Solder Temperature/Time SOL Symbol Parameter V Supply Voltage DD V Input Voltage IN T Operating Temperature OPR S1D13505 X23A-A-001-14 Table 6-1: Absolute Maximum Ratings V - 0 0 -65 to 150 260 for 10 sec. max at lead ...
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... OL 8mA (Type2) 12mA (Type3) CMOS level max 3.5 DD CMOS level min DD CMOS Schmitt 5.0V DD CMOS Schmitt, 0 5.0V DD CMOS Schmitt Page 39 Typ Max Units 400 0 1 100 200 S1D13505 X23A-A-001-14 ...
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... Low Level Input Voltage T- V Hysteresis Voltage H1 R Pull Down Resistance PD C Input Pin Capacitance I C Output Pin Capacitance O C Bi-Directional Pin Capacitance IO S1D13505 X23A-A-001-14 Condition Min Quiescent Conditions -1 -1 VDD = min I = -2mA (Type1 0.3 DD -4mA (Type2) -6mA (Type3) VDD = min ...
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... CMOS level max 2.0 DD CMOS level min DD CMOS Schmitt 3.0V DD CMOS Schmitt, 0 3.0V DD CMOS Schmitt 100 I DD Page 41 Typ Max Units 260 0 0 200 400 S1D13505 X23A-A-001-14 ...
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... A[20:0], M/R# RD/WR# t6 BS# t8 CSn# WEn# RD# RDY# D[15:0](write) D[15:0](read) Note The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is selected. S1D13505 X23A-A-001-14 = 3.0V ± 10% and V = 5.0V ± 10 for all inputs must be 5 nsec (10% ~ 90%) fall t3 t7 t12 t9 t11 t13 Figure 7-1: SH-4 Timing ...
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... Epson Research and Development Vancouver Design Center Note The SH-4 Wait State Control Register for the area in which the S1D13505 resides must be set to a non-zero value. The SH-4 read-to-write cycle transition must be set to a non-zero value (with reference to BUSCLK). Symbol t1 Clock period ...
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... RD# WAIT# D[15:0](write) D[15:0](read) Note The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is selected. Note The SH-3 Wait State Control Register for the area in which the S1D13505 resides must be set to a non-zero value. S1D13505 X23A-A-001- t12 t9 t11 ...
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... Rising edge RD# to D[15:0] tri-state (read cycle the S1D13505 host interface is disabled, the timing for WAIT# driven is relative to the fall- ing edge of CSn# or the first positive edge of CKIO after A[20:0], M/R# becomes valid, whichever one is later the S1D13505 host interface is disabled, the timing for D[15:0] driven is relative to the fall- ing edge of RD# or the first positive edge of CKIO after A[20:0], M/R# becomes valid, whichever one is later ...
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... CLK A[20:1] M/R# CS# AS# UDS# LDS# R/W# t9 DTACK# D[15:0](write) D[15:0](read) Note The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is selected. S1D13505 X23A-A-001- t12 t14 Figure 7-3: MC68000 Timing Epson Research and Development Vancouver Design Center t5 t6 t17 t11 t8 t10 ...
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... CS#, AS# or the first positive edge of CLK after A[20:1], M/R# becomes valid, whichever one is later the S1D13505 host interface is disabled, the timing for D[15:0] driven is relative to the fall- ing edge of UDS#, LDS# or the first positive edge of CLK after A[20:1], M/R# becomes valid, whichever one is later. Hardware Functional Specification ...
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... MC68K Bus 2 Interface Timing (e.g. MC68030) t1 CLK A[20:0] SIZ[1:0] M/R# CS# AS# DS# R/W# DSACK1# D[31:16](write) D[31:16](read) Note The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is selected. S1D13505 X23A-A-001- t12 t14 Figure 7-4: MC68030 Timing Epson Research and Development Vancouver Design Center t5 t6 t17 ...
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... AS# high setup to CLK 1. If the S1D13505 host interface is disabled, the timing for DSACK1# driven high is relative to the falling edge of CS#, AS# or the first positive edge of CLK after A[20:0], M/R# becomes valid, whichever one is later the S1D13505 host interface is disabled, the timing for D[31:16] driven is relative to the falling edge of UDS#, LDS# or the first positive edge of CLK after A[20:0], M/R# becomes valid, whichever one is later ...
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... PC Card Interface Timing t1 CLK t4 A[20:0] M/R# -CE[1:0] CS# -OE -WE -WAIT D[15:0](write) D[15:0](read) Note The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is selected. S1D13505 X23A-A-001- t11 Figure 7-5: PC Card Timing Epson Research and Development Vancouver Design Center t10 t13 t12 ...
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... D[15:0] setup to rising edge -WAIT (read cycle) t13 Rising edge of -OE to D[15:0] tri-state (read cycle the S1D13505 host interface is disabled, the timing for -WAIT driven low is relative to the falling edge of -OE, -WE or the first positive edge of CLK after A[20:0], M/R# becomes valid, whichever one is later. 2. ...
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... CLK t4 A[20:0] M/R# CS# RD0#,RD1# WE0#,WE1# WAIT# D[15:0](write) D[15:0](read) Note The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is selected. S1D13505 X23A-A-001- t11 Figure 7-6: Generic Timing Epson Research and Development Vancouver Design Center t10 ...
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... D[15:0] setup to rising edge WAIT# (read cycle) t13 Rising edge of RD0#,RD1# to D[15:0] tri-state (read cycle the S1D13505 host interface is disabled, the timing for WAIT# driven low is relative to the falling edge of RD0#, RD1#, WE0#, WE1# or the first positive edge of CLK after A[20:0], M/R# becomes valid, whichever one is later. 2. ...
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... BUSCLK t4 LatchA20 SA[19:0] M/R#, SBHE# CS# MEMR# MEMW# IOCHRDY SD[15:0](write) SD[15:0](read) Note The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is selected. S1D13505 X23A-A-001- t11 Figure 7-7: MIPS/ISA Timing Epson Research and Development Vancouver Design Center t10 t12 ...
Page 61
... SD[15:0] setup to rising edge IOCHRDY# (read cycle) t13 Rising edge of MEMR# toSD[15:0] tri-state (read cycle the S1D13505 host interface is disabled, the timing for IOCHRDY driven low is relative to the falling edge of MEMR#, MEMW# or the first positive edge of BUSCLK after LatchA20, SA[19:0], M/R# becomes valid, whichever one is later. 2. ...
Page 62
... Page 56 7.1.8 Philips Interface Timing (e.g. PR31500/PR31700) t1 DCLKOUT ADDR[12: ALE -CARDREG -CARDxCSH -CARDxCSL -CARDIORD -CARDIOWR -WE -RD -CARDxWAIT D[31:16](write) D[31:16](read) S1D13505 X23A-A-001- t11 t13 Figure 7-8: Philips Timing Epson Research and Development Vancouver Design Center t5 t8 t10 t12 t15 t14 Hardware Functional Specification ...
Page 63
... DCLKOUT after ADDR[12:0] becomes valid, whichever one is later the S1D13505 host interface is disabled, the timing for D[31:16] driven is relative to the falling edge of chip select or the second positive edge of DCLKOUT after ADDR[12:0] be- comes valid, whichever one is later. ...
Page 64
... Page 58 7.1.9 Toshiba Interface Timing (e.g. TX3912) t1 DCLKOUT ADDR[12: ALE CARDREG* CARDxCSH* CARDxCSL* CARDIORD* CARDIOWR* WE* RD* CARDxWAIT* D[31:16](write) D[31:16](read) S1D13505 X23A-A-001- t11 t13 Figure 7-10: Toshiba Timing Epson Research and Development Vancouver Design Center t5 t8 t10 t12 t15 t14 Hardware Functional Specification ...
Page 65
... DCLKOUT after ADDR[12:0] becomes valid, whichever one is later the S1D13505 host interface is disabled, the timing for D[31:16] driven is relative to the falling edge of chip select or the second positive edge of DCLKOUT after ADDR[12:0] be- comes valid, whichever one is later. ...
Page 66
... Power PC Interface Timing (e.g. MPC8xx, MC68040, Coldfire) t1 CLKOUT A[11:31], RD/WR# TSIZ[0:1], M/R# CS# TS# TA# BI# D[0:15](write) D[0:15](read) Note The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is selected. S1D13505 X23A-A-001- t10 t14 t17 t19 Figure 7-12: Power PC Timing Epson Research and Development ...
Page 67
... Max Units 2.5 10 S1D13505 X23A-A-001- ...
Page 68
... Input Clock Pulse Width Low PWL t Input Clock Fall Time (10 Input Clock Rise Time (10% - 90%) r Note When CLKI is more than 40MHz, REG[19h] bit 2 must be set to 1 (MCLK = CLKI/2). S1D13505 X23A-A-001- PWH PWL OSC Figure 7-13: Clock Input Requirement ...
Page 69
... MA R WE# (read) MD (read) WE#(write) MD(write) Hardware Functional Specification Issue Date: 01/02/ t10 t11 t10 t11 C1 C2 t12 t14 t15 d1 d2 t18 t20 t21 d1 d2 Figure 7-14: EDO-DRAM Read/Write Timing t7 C3 t13 t17 t16 d3 t19 t22 d3 S1D13505 X23A-A-001-14 Page 63 ...
Page 70
... Row address setup time (REG[22h] bits 3-2 = 01) Row address setup time (REG[22h] bits 3-2 = 10) Row address hold time (REG[22h] bits 3 10) t9 Row address hold time (REG[22h] bits 3-2 = 01) t10 Column address setup time t11 Column address hold time S1D13505 X23A-A-001- t10 t11 ...
Page 71
... Min Max t1- 5 0.45 t1 0.45t1 + t1- 5 X23A-A-001-14 Page 65 Units S1D13505 ...
Page 72
... RAS# pulse width (REG[22h] bit 6 and bits 3-2 = 01) RAS# pulse width (REG[22h] bit 6 and bits 3-2 = 10) t4 CAS# pulse width CAS# setup time (REG[22h] bits 3 10) t5 CAS# setup time (REG[22h] bits 3-2 = 01) S1D13505 X23A-A-001-14 t1 Clock t2 RAS CAS# Table 7-16: EDO-DRAM CAS Before RAS Refresh Timing ...
Page 73
... CAS# Hold to RAS# (REG[22h] bit 6 and bits 3-2 = 10) Hardware Functional Specification Issue Date: 01/02/02 Table 7-16: EDO-DRAM CAS Before RAS Refresh Timing Min Max Page 67 Units S1D13505 X23A-A-001-14 ...
Page 74
... RAS# to CAS# precharge time (REG[22h] bits 3 10) CAS# setup time (REG[22h] bits 3 10) t4 CAS# setup time (REG[22h] bits 3-2 = 01) CAS# precharge time (REG[22h] bits 3-2 = 00) t5 CAS# precharge time (REG[22h] bits 3 10) S1D13505 X23A-A-001-14 Stopped for Restarted for active mode suspend mode t2 ...
Page 75
... Clock RAS# CAS# MA WE#(read) MD(read) WE#(write) MD(write) Hardware Functional Specification Issue Date: 01/02/ t11 t10 t11 t8 t9 t10 t12 d1 t16 t18 t19 d1 d2 Figure 7-18: FPM-DRAM Read/Write Timing t13 t14 t15 d2 d3 t17 t20 d3 Page 69 S1D13505 X23A-A-001-14 ...
Page 76
... RAS# to CAS# delay time (REG[22h] bit and bits 3-2 = 01) t5 CAS# precharge time t6 CAS# pulse width t7 RAS# hold time Row address setup time (REG[22h] bits 3-2 = 00) t8 Row address setup time (REG[22h] bits 3-2 = 01) Row address setup time (REG[22h] bits 3-2 = 10) S1D13505 X23A-A-001- t10 t11 t21 ...
Page 77
... Table 7-18: FPM-DRAM Read/Write/Read-Write Timing 0.45 1t1 - 0.45 t1 Min Max t1- 5 0.45 t1 0.45t1 + 21 X23A-A-001-14 Page 71 Units S1D13505 ...
Page 78
... CAS# Hold to RAS# (REG[22h] bits 6 and bits 3-2 = 00) t6 CAS# Hold to RAS# (REG[22h] bits 6 and bits 3 10) CAS# Hold to RAS# (REG[22h] bits 6 and bits 3-2 = 00) CAS# Hold to RAS# (REG[22h] bits 6 and bits 3 10) S1D13505 X23A-A-001- Table 7-19: FPM-DRAM CAS Before RAS Refresh Timing 2 ...
Page 79
... CAS# setup time (CAS# before RAS# refresh) Hardware Functional Specification Issue Date: 01/02/02 Stopped for suspend mode Figure 7-21: FPM-DRAM Self-Refresh Timing Table 7-20: FPM-DRAM CBR Self-Refresh Timing Parameter Restarted for active mode Min Max X23A-A-001-14 Page 73 Units S1D13505 ...
Page 80
... SUSPEND# or LCD ENABLE BIT high to FPLINE, FPSHIFT, t5 FPDATA, DRDY active FPLINE, FPSHIFT, FPDATA, DRDY active to LCDPWR, on and t6 FPFRAME active t7 CLKI active to SUSPEND# inactive Note Where T S1D13505 X23A-A-001- Table 7-21: LCD Panel Power Off/ Power On Parameter is the period of FPFRAME and T FPFRAME ...
Page 81
... Note It is recommended that memory access not be performed after a Power Save Mode has been initiated. Hardware Functional Specification Issue Date: 01/02/02 t1 not allowed Parameter Page allowed Min Max Units 129 130 Frames 12 MCLK 8 MCLK S1D13505 X23A-A-001-14 ...
Page 82
... Diagram drawn with 2 FPLINE vertical blank period Example timing for a 320x240 panel Figure 7-24: 4-Bit Single Monochrome Passive LCD Panel Timing VDP = Vertical Display Period VNDP = Vertical Non-Display Period HDP = Horizontal Display Period HNDP = Horizontal Non-Display Period S1D13505 X23A-A-001-14 VDP LINE1 LINE2 LINE3 LINE4 LINE239 LINE240 HDP 1-1 1-5 ...
Page 83
... Hardware Functional Specification Issue Date: 01/02/ t10 t9 Parameter t11 t12 t13 t14 1 2 Min Typ Max note (note 1) 9 note 3 1 note 4 note 5 t10 + t11 4 note X23A-A-001-14 Page 77 Units S1D13505 ...
Page 84
... Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel Figure 7-26: 8-Bit Single Monochrome Passive LCD Panel Timing VDP = Vertical Display Period VNDP = Vertical Non-Display Period HDP = Horizontal Display Period HNDP = Horizontal Non-Display Period S1D13505 X23A-A-001-14 VDP LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 HDP 1-1 1-9 ...
Page 85
... Hardware Functional Specification Issue Date: 01/02/ t10 t9 t13 t14 1 Min Typ note note 3 1 note 5 t10 + t11 8 note Page 79 t8 t11 t12 2 Max Units Ts (note 1) Ts note S1D13505 X23A-A-001-14 ...
Page 86
... Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel Figure 7-28: 4-Bit Single Color Passive LCD Panel Timing VDP = Vertical Display Period VNDP = Vertical Non-Display Period HDP = Horizontal Display Period HNDP = Horizontal Non-Display Period S1D13505 X23A-A-001-14 VDP LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 HDP 1-G2 1-B3 ...
Page 87
... Hardware Functional Specification Issue Date: 01/02/ t10 Parameter t11 t12 t13 t14 1 2 Min Typ Max note (note 1) 9 note 3 1 note 4 note 5 t10 + t11 1 note 6 21 0.45 0.45 0.45 0.45 X23A-A-001-14 Page 81 Units S1D13505 ...
Page 88
... Example timing for a 640x480 panel Figure 7-30: 8-Bit Single Color Passive LCD Panel Timing (Format 1) VDP = Vertical Display Period VNDP = Vertical Non-Display Period HDP = Horizontal Display Period HNDP = Horizontal Non-Display Period S1D13505 X23A-A-001-14 VDP LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 HDP 1-R1 ...
Page 89
... Hardware Functional Specification Issue Date: 01/02/02 t1 t5a t5b t8a t9 t8b Parameter t10 t11 t12 t13 1 2 Min Typ Max note (note 1) 9 note 3 note 4 note t10 4 note 6 note X23A-A-001-14 Page 83 Units S1D13505 ...
Page 90
... Example timing for a 640x480 panel Figure 7-32: 8-Bit Single Color Passive LCD Panel Timing (Format 2) VDP = Vertical Display Period VNDP = Vertical Non-Display Period HDP = Horizontal Display Period HNDP = Horizontal Non-Display Period S1D13505 X23A-A-001-14 VDP LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 HDP 1-B3 ...
Page 91
... Hardware Functional Specification Issue Date: 01/02/ t14 Parameter t11 t10 t12 t13 1 2 Min Typ Max note (note 1) note note 4 note 5 note 6 t14 + X23A-A-001-14 Page 85 Units S1D13505 ...
Page 92
... Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel Figure 7-34: 16-Bit Single Color Passive LCD Panel Timing VDP = Vertical Display Period VNDP = Vertical Non-Display Period HDP = Horizontal Display Period HNDP = Horizontal Non-Display Period S1D13505 X23A-A-001-14 VDP LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 HDP 1-R1 1-G6 ...
Page 93
... Hardware Functional Specification Issue Date: 01/02/ t14 Parameter t10 t11 t12 t13 1 2 Min Typ Max note (note 1) note note 4 note 5 note 6 t14 + X23A-A-001-14 Page 87 Units S1D13505 ...
Page 94
... Figure 7-36: 8-Bit Dual Monochrome Passive LCD Panel Timing VDP = Vertical Display Period VNDP = Vertical Non-Display Period HDP = Horizontal Display Period HNDP = Horizontal Non-Display Period S1D13505 X23A-A-001-14 VDP LINE 1/241 LINE 2/242 LINE 3/243 LINE 4/244 LINE 239/479 LINE 240/480 HDP ...
Page 95
... Hardware Functional Specification Issue Date: 01/02/ t14 t7 Parameter t10 t11 t12 t13 1 2 Min Typ Max Units note (note 1) note note 4 note 5 note 6 t14 + X23A-A-001-14 Page S1D13505 ...
Page 96
... Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel VDP = Vertical Display Period VNDP = Vertical Non-Display Period HDP = Horizontal Display Period HNDP = Horizontal Non-Display Period S1D13505 X23A-A-001-14 VDP LINE 1/241 LINE 2/242 LINE 3/243 LINE 4/244 HDP 1-G2 1-R 1 ...
Page 97
... Ts min Hardware Functional Specification Issue Date: 01/02/ Parameter t14 t11 t10 t12 t13 1 2 Min Typ Max note (note 1) note note 4 note 5 note 6 t14 + t11 1 0.45 0.45 0.45 0.45 13 X23A-A-001-14 Page 91 Units S1D13505 ...
Page 98
... Figure 7-40: 16-Bit Dual Color Passive LCD Panel Timing VDP = Vertical Display Period VNDP = Vertical Non-Display Period HDP = Horizontal Display Period HNDP = Horizontal Non-Display Period S1D13505 X23A-A-001-14 VDP LINE 1/241 LINE 2/242 LINE 3/243 LINE 4/244 LINE 239/479 LINE 240/480 HDP ...
Page 99
... Hardware Functional Specification Issue Date: 01/02/ t14 t7 Parameter t11 t10 t12 t13 1 2 Min Typ Max Units note (note 1) note note 4 note 5 note 6 t14 + S1D13505 X23A-A-001-14 Page ...
Page 100
... R[5:1] G [5:0] B[5:1] Note: DRDY is used to indicate the first pixel Example Timing for 640x480 panel VDP = Vertical Display Period VNDP = Vertical Non-Display Period HDP = Horizontal Display Period HNDP = Horizontal Non-Display Period S1D13505 X23A-A-001-14 VNDP LINE1 HDP HNDP 1 1-1 1-2 1-1 1-2 1-1 1-2 Figure 7-42: 16-Bit TFT/D-TFD Panel Timing ...
Page 101
... Vancouver Design Center FPFRAME FPLINE FPLINE DRDY FPSHIFT R[5:1] G[5:0] B[5:1] Note: DRDY is used to indicate the first pixel Hardware Functional Specification Issue Date: 01/02/02 t9 t12 t7 t17 t11 Figure 7-43: TFT/D-TFD A.C. Timing t8 t6 t14 t13 t16 639 640 t10 X23A-A-001-14 Page 95 t15 S1D13505 ...
Page 102
... Ts min 7. t12 = [((REG[06h] bits [4:0])*8)+1] Ts min 8. t14 = [((REG[04h] bits [6:0])+1)*8] Ts min 9. t15 = [((REG[06h] bits [4:0])+1)* min 10. t17 = [((REG[05h] bits [4:0])+1)*8 - ((REG[06h] bits [4:0])+1)* min S1D13505 X23A-A-001-14 Table 7-32: TFT/D-TFD A.C. Timing Parameter Min 1 0.45 0.45 0.45 0.45 note 2 note 3 note 4 note 5 note 6 0.45 note 7 0.45 note 8 note 9 ...
Page 103
... Hardware Functional Specification Issue Date: 01/02/02 VNDP VDP LINE1 HDP HNDP 1 1-1 1-2 Figure 7-44: CRT Timing = (REG[09h] bits [1:0], REG[08h] bits [7:0 (REG[0Ah] bits [5:0 ((REG[04h] bits [6:0]) + 1)*8Ts = HNDP + HNDP = ((REG[05h] bits [4:0]) + 1)*8Ts 1 2 Page 97 LINE480 HNDP 2 1-640 S1D13505 X23A-A-001-14 ...
Page 104
... REG[08h] bits 7:0)+1) + ((REG[0Ah] bits 6:0)+1)] lines min [((REG[0Ch] bits 2:0)+1)] lines min 3. t12 = [((REG[06h] bits 4:0)+1)*8] Ts min S1D13505 X23A-A-001- Figure 7-45: CRT A.C. Timing Parameter Min Epson Research and Development Vancouver Design Center t1 Typ Max note 1 note 2 note 3 ...
Page 105
... Vancouver Design Center 8 Registers 8.1 Register Mapping The S1D13505 registers are memory mapped. The system addresses the registers through the CS#, M/R#, and AB[5:0] input pins. When CS and M/ the registers are mapped by address bits AB[5:0], e.g. REG[00h] is mapped to AB[5:0] = 000000, REG[01h] is mapped to AB[5:0] = 000001. See the table below: ...
Page 106
... Frame Buffer is disabled (REG[1Bh] bit 0 = 1), and the Ink/Cursor is inactive (Reg[27h] bits 7-6 = 00). This condition also occurs when the CRT and LCD enable bits (Reg[0Dh] bits 1-0) have remained 0 since chip reset. For further programming information, see S1D13505 Programming Notes and Examples, document number X23A-G-003-xx. ...
Page 107
... Width Size 4-bit 8-bit 16-bit Reserved MOD Rate Bit MOD Rate Bit MOD Rate Bit Page 101 RW TFT/ Passive Dual/Single LCD Panel Panel Select Select Size 9-bit 12-bit 16-bit Reserved RW MOD Rate Bit MOD Rate Bit 1 0 S1D13505 X23A-A-001-14 ...
Page 108
... The recommended minimum value which should be programmed into this register is 3 (32 pixels). The maximum value which can be programmed into this register is 1Fh, which gives a horizontal non-display period of 256 pixels. Note This register must be programmed such that REG[05h] S1D13505 X23A-A-001-14 Horizontal Horizontal Display Width Display Width ...
Page 109
... TFT/D-TFD FPLINE Polarity active high active low (REG[06h (REG[07h] bits [3:0] +1) Page 103 RW HRTC/ HRTC/ FPLINE Start FPLINE Start Position Bit 1 Position Bit 0 RW HRTC/ HRTC/ FPLINE Pulse FPLINE Pulse Width Bit 1 Width Bit 0 active low active high S1D13505 X23A-A-001-14 ...
Page 110
... When this bit = 0, a vertical display period is indicated. bits 5-0 Vertical Non-Display Period Bits [5:0] These bits specify the vertical non-display period. Vertical non-display period (lines) = Vertical Non-Display Period Bits [5: Note This register must be programmed such that REG[0Ah] S1D13505 X23A-A-001-14 Vertical Vertical Vertical Display Display Display ...
Page 111
... Page 105 RW VRTC/ VRTC/ FPFRAME FPFRAME Start Position Start Position Bit 1 Bit 0 RW VRTC/ VRTC/ FPFRAME FPFRAME Pulse Width Pulse Width Bit 1 Bit 0 TFT/D-TFD FPFRAME Polarity active low active high S1D13505 X23A-A-001-14 ...
Page 112
... Dual Panel Considerations: When configured for a dual LCD panel and using Simultaneous Display, the Half Frame Buffer Disable, REG[1Bh] bit 0, must be set to 1. This results in a lower contrast on the LCD panel, which may require adjustment. 2. The Line doubling option is not supported with dual panel. S1D13505 X23A-A-001-14 Bit-per-pixel Bit-per-pixel ...
Page 113
... Screen 1 Line Compare Bit 4 Compare Bit 3 n/a n/a Color Depth (bpp) 1 bpp 2 bpp 4 bpp 8 bpp 15 bpp 16 bpp Reserved Screen 1 Line Screen 1 Line Screen 1 Line Compare Bit 2 Compare Bit 1 Compare Bit 0 Screen 1 Line Screen 1 Line n/a Compare Bit 9 Compare Bit 8 X23A-A-001-14 Page 107 RW RW S1D13505 ...
Page 114
... Note that this is a word address. A combination of this register and the Pixel Panning register (REG[18h]) can be used to uniquely identify the start (top left) pixel within the Screen 2 image stored in the display buffer. See “Display Configuration” for details. S1D13505 X23A-A-001-14 Start Address Start Address ...
Page 115
... Pixel Panning Bits active Page 109 RW Memory Memory Address Address Offset Bit 1 Offset Bit 0 RW Memory Memory Address Address Offset Bit 9 Offset Bit 8 RW Screen 1 Screen 1 Pixel Panning Pixel Panning Bit 1 Bit 0 Bits [3:0] Bits [2:0] Bits [1:0] Bit 0 none S1D13505 X23A-A-001-14 ...
Page 116
... When this bit = 1, the panel has been powered down and the memory controller is either in self refresh mode or is performing only When this bit = 0, the chip is either powered up, in transition of powering up transition of powering down. See Section 15 Power Save Modes for details. S1D13505 X23A-A-001-14 MCLK Divide n/a ...
Page 117
... REG[31h]). For details on Frame Rate calculation see Section 14.2, “Frame Rate Calcu- lation” on page 141. Hardware Functional Specification Issue Date: 01/02/02 Table 8-10: Suspend Refresh Selection DRAM Refresh Type CAS-before-RAS (CBR) refresh Self-Refresh n/a n/a n/a Page 111 No Refresh Half Frame n/a Buffer Disable S1D13505 X23A-A-001-14 RW ...
Page 118
... When this bit = 0 (default), the GPIO2 pin is configured as an input pin. bit 1 GPIO1 Pin IO Configuration When this bit = 1, the GPIO1 pin is configured as an output pin. When this bit = 0 (default), the GPIO1 pin is configured as an input pin. S1D13505 X23A-A-001-14 MD[4] Status MD[3] Status MD[2] Status ...
Page 119
... GPO output is set to the inverse of the reset state. For information on the reset state of this pin see “Miscellaneous Interface Pin Descriptions“ on page 32 and “Summary of Power On/Reset Options“ on page 33. Hardware Functional Specification Issue Date: 01/02/02 n/a n/a n/a GPIO3 Pin GPIO2 Pin n/a IO Status IO Status n/a n/a n/a Page 113 RW n/a n/a RW GPIO1 Pin n/a IO Status RW n/a n/a S1D13505 X23A-A-001-14 ...
Page 120
... Ink/Cursor is inactive (Reg[27h] bits 7-6 = 00). This condition also occurs when the CRT and LCD enable bits (Reg[0Dh] bits 1-0) have remained 0 since chip reset. For further programming information, see S1D13505 Programming Notes and Examples, docu- ment number X23A-G-003-xx. ...
Page 121
... RAS# RCD if EDO and EDO and FPM and FPM and ASC = 1 1.5 RP RAS#-to-CAS# Delay (t ) RCD These bits specify the number X23A-A-001-14 Page 115 S1D13505 ...
Page 122
... This accelerates screen updates by allocating more memory bandwidth to CPU accesses. When this bit = 0 the display FIFO is enabled. Note For further performance increase in dual panel mode disable the half frame buffer (see section 8.2.7) and disable the cursor (see section 8.2.9). S1D13505 X23A-A-001-14 Table 8-14: RAS Precharge Timing Select ...
Page 123
... Bit 5 bits 7-0 LUT Address Bits [7:0] These 8 bits control a pointer into the Look-Up Tables (LUT). The S1D13505 has three 256-posi- tion, 4-bit wide LUTs, one for each of red, green, and blue – refer to “Look-Up Table Architecture” for details. This register selects which LUT entry is read/write accessible through the LUT Data Register (REG[26h]) ...
Page 124
... REG[28h] Cursor X Cursor X Cursor X Position Bit 7 Position Bit 6 Position Bit 5 Cursor X Position Register 1 REG[29h] Reserved n/a n/a REG[29] bit 7 Reserved This bit must be set to 0. S1D13505 X23A-A-001-14 LUT Data n/a Bit 0 Cursor High n/a Threshold Bit 3 Table 8-17: Ink/Cursor Selection REG[27h] Operating Mode Bit 7 Bit 6 0 ...
Page 125
... Cursor Color 0 Bit 12 0 Bit 11 0 Bit 10 Page 119 RW Cursor Y Cursor Y Position Bit 1 Position Bit 0 RW Cursor Y Cursor Y Position Bit 9 Position Bit 8 RW Cursor Color Cursor Color 0 Bit 1 0 Bit 0 RW Cursor Color Cursor Color 0 Bit 9 0 Bit 8 S1D13505 X23A-A-001-14 ...
Page 126
... Ink/Cursor Start Address Bits [7: 255...1 The Ink/Cursor image is stored contiguously. The address offset from the starting word of line n to the starting word of line n+1 is calculated as follows: Ink Address Offset (words) = REG[04h Cursor Address Offset (words S1D13505 X23A-A-001-14 Cursor Color Cursor Color 1 Bit 4 1 Bit 3 ...
Page 127
... Alternate Alternate FRM FRM Bit 4 Bit 3 Table 8-19: Recommended Alternate FRM Scheme Panel Mode Single Passive Alternate Alternate Alternate FRM FRM FRM Bit 2 Bit 1 Bit 0 Register Value 0000 0000 or 1111 1111 0000 0000 or 1111 1010 1111 1111 X23A-A-001-14 Page 121 RW S1D13505 ...
Page 128
... Half-Frame Buffer Image Buffer Ink/Cursor Buffer Half-Frame Buffer Image Buffer Ink/Cursor Buffer Half-Frame Buffer S1D13505 X23A-A-001-14 Table 9-1: S1D13505 Addressing M/R# Register access: • REG[00h] is addressed when AB[5: • REG[01h] is addressed when AB[5: • REG[n] is addressed when AB[5: Memory access: the 2M byte display buffer is addressed by 1 ...
Page 129
... For example, for a 640x480 8 bpp color panel the half frame buffer size is 75K bytes 512K byte display buffer, the half-frame buffer resides from 6D400h to 7FFFFh byte display buffer, the half-frame buffer resides from 1ED400h to 1FFFFFh. Hardware Functional Specification Issue Date: 01/02/ for color panel = 1 for monochrome panel Page 123 S1D13505 X23A-A-001-14 ...
Page 130
... The following diagrams show the display mode data formats for a little-endian system. 1 bpp: Byte 0 Host Address 2 bpp: Byte 0 Byte 1 Host Address 4 bpp: Byte 0 Byte 1 Byte 2 Host Address 8 bpp: Byte 0 Byte 1 Byte 2 Host Address Figure 10-1: 1/2/4/8 Bit-per-pixel Format Memory Organization S1D13505 X23A-A-001-14 bit 7 bit ...
Page 131
... Page 125 4-0 4-0 4 Panel Display 4-0 5-0 4 Panel Display S1D13505 X23A-A-001-14 ...
Page 132
... Screen 1, the remainder of the display is taken up by Screen 2 Image Buffer (REG[12h], REG[11h], REG[10h]) REG[18h] bits [3:0] Screen 1 (REG[15h], REG[14h], REG[13h]) REG[18h] bits [7:4] Screen 2 (REG[17h], REG[16h]) S1D13505 X23A-A-001-14 Display Line 0 Line 1 Screen 1 Line (REG[0Fh], REG[0Eh]) Screen 2 ((REG[04h]+1)*8) pixels Figure 10-3: Image Manipulation ...
Page 133
... Bit-per-pixel Monochrome Mode Green Look-Up Table 256x4 bit-per-pixel data from Image Buffer Figure 11-2: 2 Bit-per-pixel Monochrome Mode Data Output Path Hardware Functional Specification Issue Date: 01/02/02 4-bit Grey Data 4-bit Grey Data Page 127 S1D13505 X23A-A-001-14 ...
Page 134
... bit-per-pixel data from Image Buffer Figure 11-3: 4 Bit-per-pixel Monochrome Mode Data Output Path S1D13505 X23A-A-001-14 Epson Research and Development 0000 0001 0010 0011 0100 0101 0110 4-bit Grey Data 0111 1000 1001 1010 1011 ...
Page 135
... Blue Look-Up Table 256x4 bit-per-pixel data from Image Buffer Figure 11-4: 1 Bit-per-pixel Color Mode Data Output Path Hardware Functional Specification Issue Date: 01/02/02 4-bit Red Data 0 1 4-bit Green Data 0 1 4-bit Blue Data 0 1 Page 129 S1D13505 X23A-A-001-14 ...
Page 136
... FE FF Blue Look-Up Table 256x4 bit-per-pixel data from Image Buffer Figure 11-5: 2 Bit-per-pixel Color Mode Data Output Path S1D13505 X23A-A-001-14 Epson Research and Development 00 4-bit Red Data 4-bit Green Data 4-bit Blue Data ...
Page 137
... Green Data 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 4-bit Blue Data 0111 1000 1001 1010 1011 1100 1101 1110 1111 Page 131 S1D13505 X23A-A-001-14 ...
Page 138
... Figure 11-7: 8 Bit-per-pixel Color Mode Data Output Path 15/16 Bit-per-pixel Color Modes The LUT is bypassed and the color data is directly mapped for this color mode – See “Display Configuration” on page 124. S1D13505 X23A-A-001-14 Epson Research and Development 0000 0000 0000 0001 ...
Page 139
... Ink buffer between the image and half-frame buffers; • position a Cursor buffer between the image and half-frame buffers; • select from a multiple of Cursor buffers Panel Display S1D13505 X23A-A-001-14 Page 133 ...
Page 140
... The following diagram shows how to position a cursor. where Note There is no means to set a negative cursor position cursor must be set to a negative position, this must be dealt with through software. S1D13505 X23A-A-001- selects the color for pixel n as follows ...
Page 141
... The display is refreshed in the following sense: C–A–D–B. The application image is written to the S1D13505 in the following sense: A–B–C–D. The S1D13505 rotates and stores the application image in the following sense: C– ...
Page 142
... Increment/decrement Display Start Address register in 8 bpp mode: scroll down/ lines. • Increment/decrement Display Start Address register in 16 bpp mode: scroll down/ line. • Increment/decrement Pixel Panning register in 8 bpp or 16 bpp mode: scroll down/ line. S1D13505 X23A-A-001-14 Epson Research and Development ...
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... The following table summarizes the DRAM size requirement for SwivelView using different panel sizes and display modes. Note that DRAM size for the S1D13505 is limited to either 512K byte or 2M byte. The calculation is based on the minimum required image buffer size. The calculated minimum display buffer size is based on the image buffer and the half-frame buffer only ...
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... Hardware cursor and ink layer images are not rotated – software rotation must be used. Swivel- View must be turned off when the programmer is accessing the sprite or the ink layer. • Split screen images appear side-by-side, i.e. the portrait display is split vertically. • Pixel panning works vertically. S1D13505 X23A-A-001-14 Display Half-Frame ...
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... MCLK/3 3 MCLK/2 MCLK/2 MCLK/2 Page 139 8 bpp 16 bpp MCLK/2 MCLK/3 MCLK/2 MCLK/3 MCLK/2 MCLK/2 MCLK/3 MCLK/3 MCLK/2 MCLK/3 MCLK/2 MCLK/3 MCLK/2 MCLK/3 MCLK/2 MCLK/2 MCLK/2 MCLK/2 MCLK/3 MCLK/3 MCLK/3 MCLK/3 MCLK/2 MCLK/3 MCLK/3 MCLK/4 MCLK/3 MCLK/3 MCLK/2 MCLK/3 S1D13505 X23A-A-001-14 ...
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... Simultaneous CRT + Dual Monochrome Panel with Half Frame Buffer Enable. • Dual Color with Half Frame Buffer Enabled. • Simultaneous CRT + Dual Color Panel with Half Frame Buffer Enable. S1D13505 X23A-A-001-14 Epson Research and Development Maximum PCLK allowed N RC ...
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... PCLK Maximum Maximum Frame Minimum Pixel Rate (Hz) Panel Clock HNDP(T ) Panel s (MHz 123 56 119 32 247 40 56 242 32 243 56 232 32 471 56 441 13 123 13 X23A-A-001-14 Page 141 4 CRT S1D13505 ...
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... Dual Color with Half Frame Buffer Enabled. 1. Must set N 2. 800x600 @ 16 bpp requires 2M bytes of display buffer for all display types. 3. 800x600 @ 8 bpp on a dual color panel requires 2M bytes of display buffer if the half frame buffer is enabled. S1D13505 X23A-A-001-14 Color Depth Resolution (bpp) 1/2/4/8 2 800x600 6 ...
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... Half Frame Buffer, monochrome Hardware Functional Specification Issue Date: 01/02/02 = 4MCLKs. RC Memory access Number of MCLKs Half Frame Buffer, color Display @ 1 bpp Display @ 2 bpp Display @ 4 bpp Display @ 8 bpp Display @ 16 bpp CPU is set to 4MCLKs and the S1D13505 X23A-A-001-14 Page 143 ...
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... Percentage of non display period for single panel = (680*482 - 640*480)/680*482) = 6.2% Percentage of non display period for dual panel = (680*242 - 640*240)/680*242) = 6.6% Average Bandwidth = Percentage of non display period * Bandwidth during non display period + (1- Percentage of non display period) * Bandwidth during display period S1D13505 X23A-A-001-14 , Table 14-5: Total # MCLKs taken for Display refresh Display ...
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... Panel with Half Frame Buffer Enable. • Dual Color Panel with Half Frame Buffer Enabled. Hardware Functional Specification Issue Date: 01/02/02 Max. Pixel Maximum Bandwidth (M byte/sec) Clock 1 bpp 2 bpp 4 bpp (MHz) 40 6.67 6.67 6.67 40 6.67 6.67 6.60 20 6.67 6.67 6.67 40 6.27 5. 6.67 6.67 6.67 13.3 6.67 6.67 6.67 40 6.36 5. 6.67 6.67 6.27 13.3 6.67 6.67 6.67 33 5.5 5.5 5.5 33 5.5 5.5 5.5 16.5 5.5 5.5 5.5 33 5.17 4.21 - 16.5 5.5 5.5 5.5 11 5.5 5.5 5.5 33 5.24 4.49 - 16.5 5.5 5.5 5.5 11 5.5 5.5 5.5 Page 145 8 bpp 16 bpp 6.36 1.79 6.27 0.41 6.67 6. 6.67 3.94 6.67 6. 6.27 - 6.67 6.67 5.24 1.47 5.17 0.34 5.5 5 5.5 3.25 5.5 5 5.17 - 5.5 5.5 S1D13505 X23A-A-001-14 ...
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... Dual Monochrome with Half Frame Buffer MCLK = 25MHz Enabled. • Simultaneous CRT + Dual Monochrome Panel with Half Frame Buffer Enable. • Dual Color Panel with Half Frame Buffer Enabled. S1D13505 X23A-A-001-14 Epson Research and Development Vancouver Design Center Max. Pixel Maximum Bandwidth (M byte/sec) Clock ...
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... Epson Research and Development Vancouver Design Center 15 Power Save Modes Three power save modes are incorporated into the S1D13505 to meet the important need for power reduction in the hand-held device market. Function Display Active? Register Access Possible? Memory Access Possible? LUT Access Possible? ...
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... Page 148 16 Mechanical Data 128-pin QFP15 surface mount package 96 97 128 1 S1D13505 X23A-A-001-14 16.0 ± 0.4 14.0 ± 0.1 65 Index 32 0.4 0.16 ± 0.1 0.5 ± 0.2 Figure 16-1: Mechanical Drawing QFP15 Epson Research and Development Vancouver Design Center Unit 0~10° 1.0 Hardware Functional Specification Issue Date: 01/02/02 ...
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... S1D13505 Embedded RAMDAC LCD/CRT Controller Programming Notes and Examples Document Number: X23A-G-003-07 Copyright © 1998, 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products ...
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... Page 2 S1D13505 X23A-G-003-07 THIS PAGE LEFT BLANK Epson Research and Development Vancouver Design Center Programming Notes and Examples Issue Date: 01/02/05 ...
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... LCD Power Sequencing and Power Save Modes . . . . . . . . . . . . . . . . . . . 38 6.1 LCD Power Sequencing 6.1.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.1.2 LCD Power Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.2 Software Power Save 6.2.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.3 Hardware Power Save . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7 Hardware Cursor/Ink Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.3 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.3.1 Updating Hardware Cursor Addresses . . . . . . . . . . . . . . . . . . . . . . . . 46 Programming Notes and Examples Issue Date: 01/02/05 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . Page 3 S1D13505 X23A-G-003-07 ...
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... Page 4 7.3.2 Reg[29h] And Reg[2Bh 7.3.3 Reg [30h 7.3.4 No Top/Left Clipping on Hardware Cursor . . . . . . . . . . . . . . . . . . . . . 46 7.4 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 8 SwivelView . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 8.1 Introduction To SwivelView . . . . . . . . . . . . . . . . . . . . . . . . .47 8.2 S1D13505 SwivelView . . . . . . . . . . . . . . . . . . . . . . . . . . .47 8.3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 8.4 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 8.5 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 9 CRT Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 9.1.1 CRT Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9.1.2 Simultaneous Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10 Identifying the S1D13505 11 Hardware Abstraction Layer (HAL .53 11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 11.2 Contents of the HAL_STRUCT . . . . . . . . . . . . . . . . . . . . . . . .53 11 ...
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... Epson Research and Development Vancouver Design Center 12 Sample Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 12.1.1 Sample code using the S1D13505 HAL API . . . . . . . . . . . . . . . . . . . . . 84 12.1.2 Sample code without using the S1D13505 HAL API . . . . . . . . . . . . . . . . . 86 12.1.3 Header Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Appendix A Supported Panel Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 A.1 Supported Panel Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 Programming Notes and Examples Issue Date: 01/02/05 ...
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... Page 6 S1D13505 X23A-G-003-07 Epson Research and Development Vancouver Design Center Programming Notes and Examples Issue Date: 01/02/05 ...
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... Epson Research and Development Vancouver Design Center Table 2-1: S1D13505 Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 4-1: Look-Up Table Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 4-2: Recommended LUT Values for 1 Bpp Color Mode . . . . . . . . . . . . . . . . . . . . 22 Table 4-3: Example LUT Values for 2 Bpp Color Mode . . . . . . . . . . . . . . . . . . . . . . . 22 Table 4-4: Suggested LUT Values to Simulate VGA Default 16 Color Palette . . . . . . . . . . . 23 Table 4-5: Suggested LUT Values to Simulate VGA Default 256 Color Palette . . . . . . . . . . . 24 Table 4-6: Recommended LUT Values for 1 Bpp Gray Shade ...
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... Page 8 S1D13505 X23A-G-003-07 THIS PAGE LEFT BLANK Epson Research and Development Vancouver Design Center Programming Notes and Examples Issue Date: 01/02/05 ...
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... Figure 5-3: Screen 1 Start Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 5-4: Pixel Panning Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 5-5: 320x240 Single Panel For Split Screen . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 5-6: Screen 1 Line Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 5-7: Screen 2 Display Start Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 11-1: Components needed to build 13505 HAL application . . . . . . . . . . . . . . . . . . . 78 Programming Notes and Examples Issue Date: 01/02/05 List of Figures Page 9 S1D13505 X23A-G-003-07 ...
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... Page 10 S1D13505 X23A-G-003-07 THIS PAGE LEFT BLANK Epson Research and Development Vancouver Design Center Programming Notes and Examples Issue Date: 01/02/05 ...
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... Epson Research and Development Vancouver Design Center 1 Introduction This guide describes how to program the S1D13505 Embedded RAMDAC LCD/CRT Controller. The guide presents the basic concepts of the LCD/CRT controller and provides methods to directly program the registers. It explains some of the advanced techniques used and the special features of the S1D13505 ...
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... Page 12 2 Initialization This section describes how to initialize the S1D13505. Sample code for performing initialization of the S1D13505 is provided in the file init13505.c which is available on the internet at http://www.eea.epson.com. S1D13505 initialization can be broken into three steps. First, enable the S1D13505 controller (if necessary identify the specific controller). Next, set all the registers to their initial values ...
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... Epson Research and Development Vancouver Design Center Table 2-1: S1D13505 Initialization Sequence (Continued) Register Value [06] 0000 0000 FPLINE start position - only required for CRT or TFT/D-TFD [07] 0000 0000 FPLINE polarity set to active high [08] 1110 1111 Vertical display size = Reg[09][08 0000 0000 1110 1111 + 1 ...
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... Page 14 Table 2-1: S1D13505 Initialization Sequence (Continued) Register Value [24] 0000 0000 [26] 0000 0000 [27] 0000 0000 [28] 0000 0000 [29] 0000 0000 The remaining register control operation of the LUT and [2A] 0000 0000 hardware cursor/ink layer. During the chip initialization none of these registers needs to be set safe to write them to zero ...
Page 169
... Alternate FRM Register (REG[31h]) with the recommended value of FFh may produce more visually appealing output. For further information on the half frame buffer and the Alternate FRM Register see the S1D13505 Hardware Functional Specification, document number X23A-A-001-xx. Programming Notes and Examples Issue Date: 01/02/05 ...
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... Display Buffer Location The S1D13505 supports either a 512k byte or 2M byte display buffer. The display buffer is memory mapped and can be accessed directly by software. The memory location allocated to the S1D13505 display buffer varies with each individual hardware platform, and is determined by the OEM ...
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... Look-Up Table. Programming Notes and Examples Issue Date: 01/02/05 Bit 4 Bit 3 Bit 2 Pixel 1 Pixel 2 Pixel 2 Bit 0 Bit 1 Bit 0 Bit 4 Bit 3 Bit 2 Pixel 0 Pixel 1 Pixel 1 Bit 0 Bit 3 Bit 2 Page 17 Bit 1 Bit 0 Pixel 3 Pixel 3 Bit 1 Bit 0 Bit 1 Bit 0 Pixel 1 Pixel 1 Bit 1 Bit 0 S1D13505 X23A-G-003-07 ...
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... In eight bit-per-pixel mode each byte of display buffer represents one pixel on the display. At this color depth the read-modify-write cycles of the lessor pixel depths are eliminated. Each byte indexes into one of the 256 positions of the Look-Up Table. The S1D13505 LUT supports four bits per primary color, therefore this translates into 4096 possible colors when color mode is selected ...
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... Figure 3-6: Pixel Storage for 16 Bpp (65536 Colors/16 Gray Shades) in Two Bytes of Display Buffer In 16 bit-per-pixel mode the S1D13505 is capable of generating 65536 colors. The 65536 color pixel is divided into three parts: five bits for red, six bits for green, and five bits for blue ...
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... LUT. Refer to the S1D13505 Hardware Functional Specification, document number X23A-A-001-xx for more detail. The S1D13505 Look-Up Table is used for both the CRT and panel interface and consists of 256 indexed red/green/blue entries. Each entry is 4 bits wide. Two registers, at offsets 24h and 26h, control access to the LUT ...
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... The value inside each LUT entry represents the intensity of the given color or gray shade. This intensity can range in value between 0 and 0Fh. • The S1D13505 Look-Up Table is linear; increasing the LUT entry number results in a lighter color or gray shade. For example, a LUT entry of 0Fh into the red LUT entry will result in a bright red output while a LUT entry of 5 would result in a dull red ...
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... In color display modes, depending on the color depth, 2 through 256 index entries are used. The selection of which entries are used is automatic. 1 bpp color When the S1D13505 is configured for 1 bpp color mode, the LUT is limited to the first two entries. The two LUT entries can be any two RGB values but are typically set to black-and- white. ...
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... Epson Research and Development Vancouver Design Center 4 bpp color When the S1D13505 is configured for 4 bpp color mode the first 16 entries in the LUT are used. Each byte in the display buffer contains two adjacent pixels. The upper and lower nibbles of the byte are used as indices into the LUT. ...
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... VGA RAMDAC has six bits (64 intensities). This four to one difference has to be considered when attempting to match colors between a VGA RAMDAC and the S1D13505 LUT. (i.e. VGA levels map to LUT level 0, VGA levels map to LUT level 1...). Additionally, the significant bits of the color tables are located at different offsets within their respective bytes ...
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... S1D13505 X23A-G-003-07 Page ...
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... Table 4-6: Recommended LUT Values for 1 Bpp Gray Shade 2 bpp gray shade In 2 bpp gray shade mode the first four green elements are used to provide values to the panel. The remaining indices are unused. Table 4-7: Suggested Values for 2 Bpp Gray Shade Index S1D13505 X23A-G-003-07 Address Red Green 00 ...
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... ... Required to match CRT to panel Unused entries Page S1D13505 X23A-G-003-07 ...
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... As with 8 bpp there are limitations to the colors which can be displayed. In this mode the four most significant bits of green are used to set the absolute intensity of the image. Four bits of green resolves to 16 colors. Now however, each pixel requires two bytes. S1D13505 X23A-G-003-07 Epson Research and Development ...
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... Reducing the horizontal size makes memory available to increase the virtual vertical size. In addition to the calculated limit the virtual vertical size is limited by the size and location of the half frame buffer and the ink/cursor if present. Programming Notes and Examples Issue Date: 01/02/05 Page 2048 words. S1D13505 X23A-G-003-07 ...
Page 184
... To maintain a constant virtual width as color depth changes, the memory address offset must also change bpp each word contains 16 pixels bpp each word contains one pixel. The formula to determine the value for these registers is: offset = pixels_per_line / pixels_per_word S1D13505 X23A-G-003-07 320x240 Viewport 640x480 “ ...
Page 185
... After determining the amount of memory used by each line calculation to see if there is enough memory to support the desired number of lines. 1. Initialize the S1D13505 registers for a 320x240 panel. (See Introduction on page 11). 2. Determine the offset register value. pixels_per_word = 16 / bpp = offset = pixels_per_line / pixels_per_word = 640 / 4 = 160 words = 0A0h words Register [17h] will be written with 00h and register [16h] will be written with A0h ...
Page 186
... At color depths less than 15 bpp a second register, the pixel pan register, is required for smooth pixel level panning. Internally, the S1D13505 latches different signals at different times. Due to this internal sequence, there is an order in which the start address and pixel pan registers should be accessed during scrolling operations to provide the smoothest scrolling. Setting the registers in the wrong sequence or at the wrong time will result in a “ ...
Page 187
... Figure 5-4: Pixel Panning Register Table 5-2: Active Pixel Pan Bits Color Depth (bpp) Pixel Pan bits used 1 bits [3:0] 2 bits [2:0] 4 bits [1:0] 8 bit 0 15/ Screen 1 Screen 1 Screen 1 Pixel Pan Bit Pixel Pan Bit Pixel Pan Bit --- Page 33 S1D13505 X23A-G-003-07 ...
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... Increment the start address by the number of words per virtual line. start_address = start_address + words 3. Separate the start address value into three bytes. Write the LSB to register [10h] and the MSB to register [12h]. S1D13505 X23A-G-003-07 320x240 single panel LCD. Epson Research and Development ...
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... The Split Screen feature of the S1D13505 allows a programmer to setup a display for such an application. The figure below illustrates setting a 320x240 panel to have Image 1 displaying from scan line 0 to scan line 99 and image 2 displaying from scan line 100 to scan line 239 ...
Page 190
... While not particularly useful possible to set screen 1 and screen 2 to the same address. S1D13505 X23A-G-003-07 Start Addr ...
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... Write the screen 2 start address registers [15h], [14h] and [13h] with the values 00h, 4Bh and 00h respectively. Programming Notes and Examples Issue Date: 01/02/05 is located immediately after image 1 in the display buffer. Assume a 640x480 display and a color depth of 1 bpp. Page 37 S1D13505 X23A-G-003-07 ...
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... Option Select Bit 1 Bit 0 The LCD Enable bit triggers all automatic power sequencing. Setting the LCD Enable bit to 1 causes the S1D13505 to enable the LCD display. The following sequence of events occurs: 1. Confirms the LCD power is disabled. 2. Enables the LCD signals. 3. Counts 128 frames. ...
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... If your situation requires using the LCD Power Disable bit, see Section 6.1.2, “LCD Power Disable” on page 39 for the correct procedure. The LCD Enable bit (REG[0Dh] bit 0) should be set allow the S1D13505 to power-on the LCD using the automatic LCD Power Sequencing. ...
Page 194
... Set REG[08h (changes display height to 1 line) - This changes the display resolution to minimum (32x1). 3. Set REG[1Ah] bit Enables power save mode. 4. Wait delay time (based on new frame rate, see S1D13505 Hardware Functional Spec- ification, document number X23A-A-001-xx this time any clocks can be disabled. ...
Page 195
... The Power Save Status bit is a read-only status bit which indicates the power-save state of the S1D13505. When this bit returns a 1, the panel is powered-off and the memory suspend memory refresh mode. When this bit returns a 0, the S1D13505 is either powered- on, in transition of powering-on transition of powering-off ...
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... Page 42 6.3 Hardware Power Save The S1D13505 supports a hardware suspend power save mode. This mode is not program- mable by software controlled directly by the S1D13505 SUSPEND# pin. While hardware suspend is enabled the following conditions apply. • display(s) are inactive • registers are not-accessible • ...
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... Vancouver Design Center 7 Hardware Cursor/Ink Layer 7.1 Introduction The S1D13505 provides hardware support for a cursor or an ink layer. These features are mutually exclusive and therefore only one or the other may be active at any given time. A hardware cursor improves video throughput in graphical operating systems by off- loading much of the work typically assigned to software ...
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... When ink mode is selected these registers should be set to zero. Cursor X Position bits 9-0 determine the horizontal location of the cursor. With 10 bits of resolution the horizontal cursor range is 1024 pixels. S1D13505 X23A-G-003-07 Cursor High n/a ...
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... Position bit 8 Cursor Color Cursor Color 0 bit 1 0 bit 0 Cursor Color Cursor Color 0 bit 9 0 bit 8 Cursor Color Cursor Color 1 bit 1 1 bit 0 Cursor Color Cursor Color 1 bit 9 1 bit 8 Ink/Cursor Ink/Cursor Start Address Start Address bit 1 bit 0 S1D13505 X23A-G-003-07 ...
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... No Top/Left Clipping on Hardware Cursor The S1D13505 does not clip the hardware cursor on the top or left edges of the display. For cursor shapes where the hot spot is not the upper left corner of the image (the hourglass for instance), the cursor image will have to be modified to clip the cursor shape. ...