S1D13505 Epson Electronics America, Inc., S1D13505 Datasheet - Page 5

• Manufacturer Part Number: S1D13505
• Description: LCD Controller
• Manufacturer: Epson Electronics America, Inc.

S1D13505 EMBEDDED RAMDAC LCD/CRT CONTROLLER
The S1D13505 is a color/monochrome LCD/CRT graphics controller interfacing to a wide range of CPUs and display
devices. The S1D13505 architecture is designed to meet the low cost, low power requirements of the embedded
markets, such as Mobile Communications, Hand-Held PCs, and Office Automation.
The S1D13505 supports multiple CPUs, all LCD panel types, CRT, and additionally provides a number of
differentiating features. Products requiring a “Portrait” mode display can take advantage of the SwivelView feature.
Simultaneous, Virtual and Split Screen Display are just some of the display modes supported, while the Hardware
Cursor, Ink Layer, and the Memory Enhancement Registers offer substantial performance benefits. These features,
combined with the S1D13505’s Operating System independence, make it an ideal display solution for a wide variety
of applications.
Memory Interface
CPU Interface
Display Support
X23A-C-002-15
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DESCRIPTION
FEATURES
16-bit EDO-DRAM or FPM-DRAM interface.
Memory size options:
Addressable as a single linear address space.
Supports the following interfaces:
CPU write buffer.
4/8-bit monochrome passive LCD interface.
4/8/16-bit color passive LCD interface.
Single-panel, single-drive displays.
Dual-panel, dual-drive displays.
Direct support for 9/12-bit TFT/D-TFD; 18-bit TFT/D-TFD
is supported up to 64K color depth (16-bit data).
Embedded RAMDAC with direct analog CRT drive.
Simultaneous display of CRT and passive or TFT/D-TFD
panels.
Maximum resolution of 800x600 pixels at a color
depth of 16 bpp.
512K bytes using one 256K 16 device.
2M bytes using one 1M 16 device.
Hitachi SH-4.
Hitachi SH-3.
Motorola M68K.
Philips MIPS PR31500/PR31700.
Toshiba MIPS TX3912.
Motorola Power PC MPC821.
NEC MIPS VR4102/VR4111.
Epson E0C33.
PC Card (PCMCIA).
StrongARM (PC Card).
ISA bus.
MPU bus interface with programmable READY.
S AV I N G
ENERGY
EPSON
Display Modes
Clock Source
Power Down Modes
General Purpose IO Pins
Operating Voltage
Package
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1/2/4/8/16 bit-per-pixel (bpp) support on LCD/CRT.
Up to 16 shades of gray using FRM on monochrome
passive LCD panels.
Up to 4096 colors on passive LCD panels.
Up to 64K colors on active matrix TFT/D-TFD LCD
panels and CRT in 16 bpp modes.
Split Screen Display: allows two different images to be
simultaneously viewed on the same display.
Virtual Display Support: displays images larger than the
display size through the use of panning.
Double Buffering/multi-pages: provides smooth
animation and instantaneous screen update.
SwivelView: direct hardware 90° rotation of
Acceleration of screen updates by allocating full
display memory bandwidth to CPU.
Hardware 64x64 pixel 2-bit cursor or full screen
2-bit ink layer.
Single clock input for both pixel and memory clocks.
Memory clock can be input clock or (input clock/2),
providing flexibility to use CPU bus clock as input.
Pixel clock can be memory clock or (memory clock/2) or
(memory clock/3) or (memory clock/4).
Software power save mode.
LCD power sequencing.
Up to 3 General Purpose IO pins are available.
2.7 volts to 5.5 volts.
128-pin QFP15 surface mount package.
display image for portrait mode display.
GRAPHICS
S1D13505
October 2001
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