S1D13505 Epson Electronics America, Inc., S1D13505 Datasheet - Page 61

• Manufacturer Part Number: S1D13505
• Description: LCD Controller
• Manufacturer: Epson Electronics America, Inc.

Epson Research and Development
Vancouver Design Center
Hardware Functional Specification
Issue Date: 01/02/02
Symbol
t11
t10
t12
t13
t7
t1
t2
t3
t4
t5
t6
t8
t9
1
2
Clock period
Clock pulse width high
Clock pulse width low
LatchA20, SA[19:0], M/R#, SBHE# setup to first BUSCLK where
CS# = 0 and either MEMR# = 0 or MEMW# = 0
LatchA20, SA[19:0], M/R#, SBHE# hold from rising edge of
either MEMR# or MEMW#
CS# hold from rising edge of either MEMR# or MEMW#
Falling edge of either MEMR# or MEMW# to IOCHRDY# driven
low
Rising edge of either MEMR# or MEMW# to IOCHRDY# tri-state
SD[15:0] setup to third BUSCLK where CS# = 0 MEMW# = 0
(write cycle)
SD[15:0] hold (write cycle)
Falling edge MEMR# to SD[15:0] driven (read cycle)
SD[15:0] setup to rising edge IOCHRDY# (read cycle)
Rising edge of MEMR# toSD[15:0] tri-state (read cycle)
1.
2.
If the S1D13505 host interface is disabled, the timing for IOCHRDY driven low is relative to
the falling edge of MEMR#, MEMW# or the first positive edge of BUSCLK after LatchA20,
SA[19:0], M/R# becomes valid, whichever one is later.
If the S1D13505 host interface is disabled, the timing for SD[15:0] driven is relative to the
falling edge of MEMR# or the first positive edge of BUSCLK after LatchA20, SA[19:0],
M/R# becomes valid, whichever one is later.
Parameter
Table 7-7: MIPS/ISA Timing
Min
20
10
10
6
6
0
0
0
5
0
0
0
5
3.0V
Max
25
25
Min
2.5
20
10
10
6
6
0
0
0
0
0
0
5
5.0V
Max
10
10
X23A-A-001-14
S1D13505
Units
Page 55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns