S1D13505 Epson Electronics America, Inc., S1D13505 Datasheet - Page 99

• Manufacturer Part Number: S1D13505
• Description: LCD Controller
• Manufacturer: Epson Electronics America, Inc.

Epson Research and Development
Vancouver Design Center
1.
2.
3.
4.
5.
6.
Hardware Functional Specification
Issue Date: 01/02/02
Symbol
t10
t11
t12
t13
t14
Ts
t1
t3
t5
t6
t7
t1
t2
t3
t4
t5
t6
t7
t8
t9
min
min
min
min
min
= pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0])
= t3
= [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8] + 33 Ts
= [(((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8)-1] Ts
= [((REG[05h] bits [4:0]) + 1)*8 - 20] Ts
= [((REG[05h] bits [4:0]) + 1)*8 - 11] Ts
Data Timing
Sync Timing
FPFRAME setup to FPLINE pulse trailing edge
FPFRAME hold from FPLINE pulse trailing edge
FPLINE period
FPLINE pulse width
MOD transition to FPLINE pulse trailing edge
FPSHIFT falling edge to FPLINE pulse leading edge
FPSHIFT falling edge to FPLINE pulse trailing edge
FPLINE pulse trailing edge to FPSHIFT falling edge
FPSHIFT period
FPSHIFT pulse width low
FPSHIFT pulse width high
UD[7:0], LD[7:0] setup to FPSHIFT falling edge
UD[7:0], LD[7:0] hold to FPSHIFT falling edge
FPLINE pulse trailing edge to FPSHIFT rising edge
min
- 14Ts
FPFRAME
FPSHIFT
UD[7:0]
LD[7:0]
FPLINE
FPLINE
MOD
Figure 7-41: 16-Bit Dual Color Passive LCD Panel A.C. Timing
Table 7-31: 16-Bit Dual Color Passive LCD Panel A.C. Timing
Parameter
t5
t6
t7
t1
t14
t4
t8
t2
t12
1
t14 + 2
note 2
note 3
note 5
note 6
Min
t13
t3
14
12
9
1
2
1
1
1
1
t11
t9
2
Typ
t10
note 4
Max
X23A-A-001-14
Ts (note 1)
S1D13505
Units
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Page 93